Page 3 - Contents
Intel ® 440GX AGPset Design Guide iii Contents 1 Introduction ................................................................................................................1-1 1.1 About This Design Guide ..............................................................................1-1 1.2 Referenc...
Page 7 - Figures
Intel ® 440GX AGPset Design Guide vii Figures 1-1 Intel ® Pentium ® II Processor / Intel ® 440GX AGPset System Block Diagram..................................................................................1-4 2-1 Major Signal Sections (82443GX Top View).................................................
Page 8 - Tables
viii Intel ® 440GX AGPset Design Guide Tables 2-1 Recommended Trace Lengths for Single Processor Design ........................ 2-7 2-2 Recommended Trace Lengths for Dual Processor Designs2 ....................... 2-8 2-3 SET Trace Length Requirements ..................................................
Page 9 - Revision History
Intel ® 440GX AGPset Design Guide ix Revision History Date Revision Description 3/99 -001 Initial Release.
Page 11 - Introduction
Page 13 - About This Design Guide
Intel ® 440GX AGPset Design Guide 1-1 Introduction Introduction 1 This document provides design guidelines for developing Intel ® Pentium ® II processor / Intel ® 440GX AGPset based systems. Motherboard and memory subsystem design guidelines are covered. Special design recommendations and concerns a...
Page 14 - References
Intel ® 440GX AGPset Design Guide 1-2 Introduction 1.2 References • Intel ® Pentium ® II Processor Datasheet • Intel ® 440GX AGPset Datasheet (WWW; order number 290638) • Intel 82371EB PCI-to-ISA/IDE Xcelerator (PIIX4) Datasheet (WWW; order number 290562) • Intel Architecture Software Developer’s Ma...
Page 16 - Pentium
Intel ® 440GX AGPset Design Guide 1-4 Introduction Intel introduced the Intel ® Pentium ® II processor as 350/100 and 400/100 speeds with 512 KB L2 cache versions. 1.3.2 Intel ® 440GX AGPset • The Intel ® 440GX AGPset is the fourth generation chipset based on the Intel ® Pentium ® Pro processor arch...
Page 17 - System Bus Interface
Intel ® 440GX AGPset Design Guide 1-5 Introduction Figure 1-1 shows a block diagram of a typical platform based on the Intel ® 440GX AGPset. The 82443GX system bus interface supports up to two Intel ® Pentium ® II processors at the maximum bus frequency of 100 MHz. The physical interface design is b...
Page 18 - PCI Interface
Intel ® 440GX AGPset Design Guide 1-6 Introduction 1.3.2.4 PCI Interface The 82443GX PCI interface is 33 MHz Revision 2.1 compliant and supports up to five external PCI bus masters in addition to the I/O bridge (PIIX4E). 1.3.2.5 System Clocking The 82443GX operates the system bus interface at 100 MH...
Page 20 - Power Management; Design Recommendations; Voltage Definitions
Intel ® 440GX AGPset Design Guide 1-8 Introduction 1.3.3.3 Remote Wake-Up If a PC supports a reduced power state, it must be possible to bring the system to a fully powered state in which all management interfaces are available. Typically, the LAN adapter recognizes a special packet as a signal to w...
Page 21 - General Design Recommendations
Intel ® 440GX AGPset Design Guide 1-9 Introduction 1.4.2 General Design Recommendations 1. Intel recommends using an industry standard programmable Voltage Regulator Module (VRM) installed in a VRM header or an onboard programmable voltage regulator designed for Intel ® Pentium ® II processors. 2. S...
Page 23 - Motherboard Design
Page 25 - Motherboard Layout and Routing Guidelines; BGA Quadrant Assignment
Intel ® 440GX AGPset Design Guide 2-1 Motherboard Layout and Routing Guidelines Motherboard Layout and Routing Guidelines 2 This chapter describes layout and routing recommendations to insure a robust design. Follow these guidelines as closely as possible. Any deviations from the guidelines listed h...
Page 26 - Figure 2-2. Example ATX Placement for a UP Pentium
Motherboard Layout and Routing Guidelines 2-2 Intel ® 440GX AGPset Design Guide Figure 2-2 and Figure 2-3 show the proposed component placement for a single processor for both ATX and NLX form factor designs. ATX Form Factor: 1. The ATX placement and layout below is recommended for single (UP) Intel...
Page 27 - Board Description; Figure 2-3. Example NLX Placement for a UP Intel
Intel ® 440GX AGPset Design Guide 2-3 Motherboard Layout and Routing Guidelines NLX Form Factor: 1. The NLX placement and layout below is recommended for a single (UP) Intel ® Pentium ® II processor / Intel ® 440GX AGPset system design. 2. The example placement below shows one Slot 1 connector, 4 DI...
Page 29 - Routing Guidelines
Intel ® 440GX AGPset Design Guide 2-5 Motherboard Layout and Routing Guidelines Additional guidelines on board buildup, placement and layout include: • For a 4-layer single processor design, double ended termination is recommended for GTL+ signals. One termination resistor is present on the processo...
Page 30 - GTL+ Layout Recommendations; Single Processor Design; Single Processor Network Topology and Conditions; Figure 2-7. Recommended Topology for Single Processor Design
Motherboard Layout and Routing Guidelines 2-6 Intel ® 440GX AGPset Design Guide 2.3.1 GTL+ Description GTL+ is the electrical bus technology used for the Intel ® Pentium ® Pro processor and Intel ® Pentium ® II processor system bus. GTL+ is a low output swing, incident wave switching, open- drain bu...
Page 31 - Single Processor Recommended Trace Lengths; Table 2-1. Recommended Trace Lengths for Single Processor Design
Intel ® 440GX AGPset Design Guide 2-7 Motherboard Layout and Routing Guidelines 2.3.3.2 Single Processor Recommended Trace Lengths Single processor trace length recommendations are summarized in Table 2-1 . The recommended lengths are derived from the parametric sweeps and Monte Carlo analysis descr...
Page 32 - Dual Processor Systems; Dual Processor Network Topology and Conditions; Set Network Topology and Conditions; Figure 2-9. Recommended Topology for Dual Processor Design; Table 2-2. Recommended Trace Lengths for Dual Processor Designs
Motherboard Layout and Routing Guidelines 2-8 Intel ® 440GX AGPset Design Guide 2.3.4 Dual Processor Systems 2.3.4.1 Dual Processor Network Topology and Conditions 2.3.4.2 Dual Processor Recommended Trace Lengths The recommended trace lengths for dual processor designs are summarized in Table 2-2 . ...
Page 33 - SET Trace Length Requirements
Intel ® 440GX AGPset Design Guide 2-9 Motherboard Layout and Routing Guidelines In the SET topology, the only termination is on the Intel ® Pentium ® II processor substrate. There is no termination present at the other end of the network. Due to the lack of termination, SET exhibits much more ringba...
Page 34 - Additional Guidelines; Minimizing Crosstalk
Motherboard Layout and Routing Guidelines 2-10 Intel ® 440GX AGPset Design Guide 2.3.6 Additional Guidelines 2.3.6.1 Minimizing Crosstalk The following general rules will minimize the impact of crosstalk in the high speed GTL+ bus design: • Maximize the space between traces. Maintain a minimum of 0....
Page 35 - Design Methodology
Intel ® 440GX AGPset Design Guide 2-11 Motherboard Layout and Routing Guidelines 2.3.7 Design Methodology Intel recommends using the following design methodology when designing systems based on one or two Intel ® Pentium ® II processors and one Intel ® 440GX AGPset. The methodology evolved from Inte...
Page 36 - Performance Requirements
Motherboard Layout and Routing Guidelines 2-12 Intel ® 440GX AGPset Design Guide 2.3.8 Performance Requirements Prior to performing interconnect simulations, establish the minimum and maximum flight time requirements. Setup and hold requirements determine the flight time bounds for the host bus. The...
Page 37 - Topology Definition; Table 2-4. Recommended 100 MHz System Flight Time Specs
Intel ® 440GX AGPset Design Guide 2-13 Motherboard Layout and Routing Guidelines Section 2.7, “Timing Analysis” on page 2-17 describes the timing analysis for the 100 MHz host bus in more detail. Table 2-4 provides recommended flight time specifications for single and dual Intel ® Pentium ® II proce...
Page 38 - Post-Layout Simulation
Motherboard Layout and Routing Guidelines 2-14 Intel ® 440GX AGPset Design Guide The methodology that Intel recommends is known as “Sensitivity Analysis”. In sensitivity analysis, interconnect parameters are varied to understand how they affect system timing and signal integrity. Sensitivity analysi...
Page 39 - Crosstalk and the Multi-Bit Adjustment Factor; Validation; Flight Time Measurement
Intel ® 440GX AGPset Design Guide 2-15 Motherboard Layout and Routing Guidelines 2.5.1 Crosstalk and the Multi-Bit Adjustment Factor Coupled lines should be included in the post-layout simulations. The flight times listed in Table 2-4 apply to single bit simulations only. They include an allowance f...
Page 40 - Signal Quality Measurement; Table 2-6. Ringback Guidelines at the Intel
Motherboard Layout and Routing Guidelines 2-16 Intel ® 440GX AGPset Design Guide 2.6.2 Signal Quality Measurement Signal integrity is specified at the processor core, which is not accessible. Intel has found that there can be substantial miscorrelation between ringback at the edge finger versus the ...
Page 41 - Timing Analysis
Intel ® 440GX AGPset Design Guide 2-17 Motherboard Layout and Routing Guidelines 2.7 Timing Analysis To determine the available flight time window perform an initial timing analysis. Analysis of setup and hold conditions will determine the minimum and maximum flight time bounds for the host bus. Use...
Page 42 - Table 2-10. Recommended 100 MHz System Timing Parameters; Table 2-11. Recommended 100 MHz System Flight Time Specs
Motherboard Layout and Routing Guidelines 2-18 Intel ® 440GX AGPset Design Guide Notice that the timing equations include an extra term to account for the delay due to routing of the BCLK trace on the processor substrate from the processor edge fingers and the processor core. Adding the BCLK adjustm...
Page 43 - AGP Layout and Routing Guidelines; AGP Connector (“Up Option) Layout Guidelines; Figure 2-14. AGP Connector Layout Guidelines
Intel ® 440GX AGPset Design Guide 2-19 Motherboard Layout and Routing Guidelines 2.8 AGP Layout and Routing Guidelines For the definition of AGP Interface functionality (protocols, rules and signaling mechanisms, as well as the platform level aspects of AGP functionality), refer to the latest AGP In...
Page 44 - Table 2-13. Source Synchronous Motherboard Recommendations
Motherboard Layout and Routing Guidelines 2-20 Intel ® 440GX AGPset Design Guide It is always best to reduce the line length mismatch wherever possible to insure added margin. It is also best to separate the traces by as much as possible to reduce the amount of trace to trace coupling. The clock lin...
Page 45 - Table 2-15. Source Synchronous Motherboard Recommendations
Intel ® 440GX AGPset Design Guide 2-21 Motherboard Layout and Routing Guidelines For trace lengths that are between 1.0 inch and 4.5 inches, a 1:1 trace spacing is recommended for data lines. The strobe requires a 1:2 trace spacing. This is for designs that require less than 4.5 inches between the A...
Page 47 - Matching the Reference Planes; Figure 2-17. Registered SDRAM DIMM Example
Intel ® 440GX AGPset Design Guide 2-23 Motherboard Layout and Routing Guidelines There are also “population” rules which need to be observed. To properly adjust memory timings for 100 MHz operation, it is asked of the OEM and end user to populate the motherboard starting with the DIMM located the fu...
Page 48 - Trace Width vs. Trace Spacing; Memory Layout & Routing Guidelines
Motherboard Layout and Routing Guidelines 2-24 Intel ® 440GX AGPset Design Guide 2.9.1.3 Trace Width vs. Trace Spacing To minimize the crosstalk, a 1:2 trace width vs. trace spacing routing (e.g., 6 mils on 9 mils or 5 mils on 10 mils) should be used for all memory interface signals. 2.9.2 Memory La...
Page 54 - PCI Bus Routing Guidelines
Motherboard Layout and Routing Guidelines 2-30 Intel ® 440GX AGPset Design Guide 2.9.3 4 DIMM Routing Guidelines [NO FET] 2.9.4 PCI Bus Routing Guidelines The 82443GX provides a PCI Bus interface that is compliant with the PCI Local Bus Specification. The implementation is optimized for high-perform...
Page 55 - Decoupling Guidelines: Intel; H o s t B r i d g e
Intel ® 440GX AGPset Design Guide 2-31 Motherboard Layout and Routing Guidelines Because of the specifics of an ATX layout, it is recommended that the PIIX4E component is at the “END” of the PCI bus, as shown in Figure 2-28 . This insures proper “termination” of the PCI Bus signals. 2.9.5 Decoupling...
Page 56 - Clock Routing Spacing; System Bus Clock Layout; Figure 2-30. Clock Trace Spacing Guidelines
Motherboard Layout and Routing Guidelines 2-32 Intel ® 440GX AGPset Design Guide 2.9.6 Intel ® 440GX AGPset Clock Layout Recommendations 2.9.6.1 Clock Routing Spacing A Intel ® Pentium ® II processor / Intel ® 440GX AGPset platform requires a clock synthesizer for supplying 100 MHz system bus clocks...
Page 57 - PCI Clock Layout
Intel ® 440GX AGPset Design Guide 2-33 Motherboard Layout and Routing Guidelines 2.9.6.3 PCI Clock Layout PCI clock nets should be routed a point-to-point connections with a 22 Ohm series resistor that is to be placed as close to the output pins on the clock driver as possible (<0.5”). Layout gui...
Page 58 - AGP Clock Layout
Motherboard Layout and Routing Guidelines 2-34 Intel ® 440GX AGPset Design Guide 2.9.6.5 AGP Clock Layout Series Termination: 22 Ohm series termination should be used for the AGP clocks. Layout guidelines: The feedback clock trace length equals the standard clock motherboard trace length plus the ca...
Page 59 - Design Checklist
Page 61 - Overview
Intel ® 440GX AGPset Design Guide 3-1 Design Checklist Design Checklist 3 3.1 Overview The following checklist is intended to be used for schematic reviews of Intel ® 440GX AGPset desktop designs. It does not represent the only way to design the system, but provides recommendations based on the Inte...
Page 67 - Slot 1 Decoupling Capacitors
Intel ® 440GX AGPset Design Guide 3-7 Design Checklist 3.3.4 Uni-Processor (UP) Slot 1 Checklist • A UP system must connect BREQ0# of the Slot 1 connector to the 82443GX’s BREQ0# signal. This will assign an agent ID of 0 to the processor. BREQ1# on the Slot 1 connector is left as a no connect. • For...
Page 69 - CKBF - SDRAM 1 to 18 Clock Buffer; GCKE and DCLKWR Connection
Intel ® 440GX AGPset Design Guide 3-9 Design Checklist 3.4.2 CKBF - SDRAM 1 to 18 Clock Buffer • A 4.7K ohm pull-up to VCC 3.3 on the OE pin is needed to enable the buffer. • Note that DCLKRD pin has been changed to a no connect (NC). The DCLKRD functionality has been combined with DCLKWR. If desire...
Page 74 - SDRAM Connections
Intel ® 440GX AGPset Design Guide 3-14 Design Checklist 3.6 Intel ® 440GX AGPset Memory Interface 3.6.1 SDRAM Connections NOTES: 1. Some of the pin ranges above are dependent on which DIMM is being reviewed. “x” and “y” indicate signal copies. 2. MAAxx address lines need to be routed to the two DIMM...
Page 75 - DIMM Solution With FET Switches; Registered SDRAM; Figure 3-3. Current Solution With Existing FET Switches; F E T
Intel ® 440GX AGPset Design Guide 3-15 Design Checklist 3.6.2 DIMM Solution With FET Switches • With existing 64Mbit technology, 512 MB, 1 GB and 2 GB support for servers and workstations must have 4 double sided DIMMs. • 500 ohm - 1K ohm pull-down resistors on each of the second inputs (1A2, 2A2, e...
Page 76 - PIIX4E Connections
Intel ® 440GX AGPset Design Guide 3-16 Design Checklist 3.7 82371EB (PIIX4E) 3.7.1 PIIX4E Connections Table 3-7. PIIX4E Connectivity (Sheet 1 of 4) Signal Names Connection 48MHz Connect to CK100 through a 22 ohm series resistor. A20GATE Connected to SIO. 8.2K ohm pull-up to VCC3. A20M# Part of CPU/b...
Page 80 - IDE Routing Guidelines; Cabling; Motherboard
Intel ® 440GX AGPset Design Guide 3-20 Design Checklist 3.7.2 IDE Routing Guidelines This section contains guidelines for connecting and routing the PIIX4E IDE interface. The PIIX4E has two independent IDE channels. This section provides guidelines for IDE connector cabling and motherboard design, i...
Page 81 - P I I X 4 E
Intel ® 440GX AGPset Design Guide 3-21 Design Checklist One resistor per IDE connector is recommended for all signals. For signals labeled as 22-47 Ω , the correct value should be determined for each unique motherboard design, based on signal quality. RESET comes from the PIIX4E RSTDRV signal throug...
Page 82 - PIIX4E Power And Ground Pins; PCI Bus Signals
Intel ® 440GX AGPset Design Guide 3-22 Design Checklist 3.7.3 PIIX4E Power And Ground Pins • Vcc, Vcc(RTC), Vcc(SUS), and Vcc(USB) must be tied to 3.3V. • V REF must be tied to 5V in a 5V tolerant system. This signal must be power up before or simultaneous to Vcc, and it must be power down after or ...
Page 83 - ISA Signals
Intel ® 440GX AGPset Design Guide 3-23 Design Checklist Third, if the design currently uses an in-line active gate/buffer on PCIRST# to drive the PCI bus, consider removal of this gate/buffer entirely. The PIIX4/PIIX4E is designed to drive the entire PCI bus. 3.9 ISA Signals 3.10 ISA and X-Bus Signa...
Page 84 - USB Interface
Intel ® 440GX AGPset Design Guide 3-24 Design Checklist 3.11 USB Interface • Contact your local Intel Field Sales representative for the following Application Note: 82371AB PIIX4 Application Note #1: USB Design Guide And Checklist Rev 1.1. This document discusses details of the PIIX4/PIIX4E implemen...
Page 85 - Flash Design; Dual-Footprint Flash Design
Intel ® 440GX AGPset Design Guide 3-25 Design Checklist 3.13 Flash Design 3.13.1 Dual-Footprint Flash Design New features are coming to the PC continue to increase the size of BIOS code, pushing the limits of the 1 Mbit boundary. OEMs have already converted many PC designs to 2 Mbit BIOS and higher,...
Page 86 - Figure 3-6. nterfacing Intel’s Flash with PIIX4E in Desktop; P I I X 4
Intel ® 440GX AGPset Design Guide 3-26 Design Checklist Following are general layout guidelines for using the Intel’s boot block flash memories (28F001GX/28F002BC) in the system: • If adding a switch on VPP for write protection, switch to GND instead of VCC. • Connect the DU pin of the 2Mbit devices...
Page 88 - System and Test Signals; Figure 3-7. Interfacing Intel’s Flash with PIIX4E in Desktop
Intel ® 440GX AGPset Design Guide 3-28 Design Checklist 3.14 System and Test Signals • 8.2K ohm pull-up resistor is recommended on the TEST# pin of the PIIX4E. 3.15 Power Management Signals • A power button is required by the ACPI specification. • PWRBTN# is connected to the front panel on/off power...
Page 90 - Power Button Implementation
Intel ® 440GX AGPset Design Guide 3-30 Design Checklist • The system reset button has typically been connected indirectly to the PWROK input of the PIIX4/PIIX4E. This technique will not reset the suspend well logic, which includes the SMBus Host and Slave controllers. To reset the hardware in the su...
Page 91 - Miscellaneous
Intel ® 440GX AGPset Design Guide 3-31 Design Checklist • Poll the power button status bit during POST while SMIs are not loaded and go directly to soft-off if it gets set. • Always install an SMI handler for the power button that operates until ACPI is enabled. • Emergency Override: Pressing the po...
Page 93 - Manageability Devices; LM79 Microprocessor System Hardware Monitor
Intel ® 440GX AGPset Design Guide 3-33 Design Checklist PIIX4E. For ACPI compliance, this signal must be connected to the IOAPIC. There are two different routing options: — INTIN9: IRQ9OUT# can be connected to INTIN9 on the IOAPIC. The ACPI BIOS will report to the OS that the SCI uses IRQ9 for both ...
Page 95 - USB and Multi-processor BIOS
Intel ® 440GX AGPset Design Guide 3-35 Design Checklist 3.18.4 Wake On LAN (WOL) Header • A 3-pin WOL header interconnects the NIC and motherboard, and requires a 5VSB to pin1. • The WOL supports the MP_Wakeup pulse, allowing it to turn on the system via a signal pulse. The LID input on the PIIX4E r...
Page 96 - Thermals / Cooling Solutions; Design Considerations; Mechanicals
Intel ® 440GX AGPset Design Guide 3-36 Design Checklist 3.19.2 Design Considerations • For UP systems to support both the current Intel ® Pentium ® II processor and future processors, it is highly recommended that storage space for two (or more) BIOS Updates be provided. This will allow manufacturin...
Page 97 - Electricals
Intel ® 440GX AGPset Design Guide 3-37 Design Checklist 3.21.1 Design Considerations • The Intel ® Pentium ® II processor retention mechanism, retention mechanism attach mount and heat sink support is an optional support structure for retaining the Slot 1 processor in the system during shock and vib...
Page 98 - Layout Checklist; Routing and Board Fabrication; Applications and Add-in Hardware; Design Consideration
Intel ® 440GX AGPset Design Guide 3-38 Design Checklist 3.23 Layout Checklist 3.23.1 Routing and Board Fabrication • VRM 8.2 Support: Is the Vcc CORE trace/power plane sufficient to ensure Vcc CORE meets specification. See the Intel ® Pentium ® II Datasheet for trace/power plane resistance and lengt...
Page 101 - Debug Recommendations; Slot 1 Test Tools; Debug/Simulation Tools
Intel ® 440GX AGPset Design Guide 4-1 Debug Recommendations Debug Recommendations 4 This chapter provides tool information, logic suggestions, technical support options and a summary of the problems which have been found to be associated with system debug. Although not comprehensive in scope, the re...
Page 102 - FLO; THERM; Debug Features
Intel ® 440GX AGPset Design Guide 4-2 Debug Recommendations Contact your local Intel Field Sales representative to complete the proper software license agreement and non-disclosure agreement required to receive the ITP. 4.2.3 Bus Functional Model (BFM) A bus functional model for the Intel ® Pentium ...
Page 104 - Debug Logic Recommendations
Intel ® 440GX AGPset Design Guide 4-4 Debug Recommendations Inputs to the Slot 1 connector, from system logic (assuming a 14mA driver): • PWRGOOD 150 - 330 ohm • INIT# 150 - 330 ohm • LINT[0]/INTR 150 - 330 ohm • LINT[1]/NMI 150 - 330 ohm • IGNNE# 150 - 330 ohm • A20M# 150 - 330 ohm Bi-directional s...
Page 105 - Debug Considerations; Debug Layout; Debug Procedures
Intel ® 440GX AGPset Design Guide 4-5 Debug Recommendations 4.3.2.1 Debug Considerations • As technology drives better low power modes, the Vcc CORE current demand could approach 0 Amps. This may cause a regulator to go out of regulation. Place pads for a load resistance on the Vcc CORE regulator in...
Page 107 - Third Party Vendors
Page 109 - Third-Party Vendor Information; Processors
Intel ® 440GX AGPset Design Guide 5-1 Third-Party Vendor Information Third-Party Vendor Information 5 This design guide has been compiled to give an overview of important design considerations while providing sources for additional information. This chapter includes information regarding various thi...
Page 110 - Voltage Regulator Modules; Voltage Regulator Control Silicon; Table 5-5. Voltage Regulator Control Silicon Vendors
Intel ® 440GX AGPset Design Guide 5-2 Third-Party Vendor Information 5.1.1 Voltage Regulator Modules The following vendors are developing DC-DC converter modules for Intel ® Pentium ® II processor voltage and current requirements per the VRM 8.2 DC-DC Converter Design Guidelines. 5.1.2 Voltage Regul...
Page 111 - Clock Drivers; Power Management Components; Table 5-7. Power Management Component Vendors
Intel ® 440GX AGPset Design Guide 5-3 Third-Party Vendor Information 5.2 Intel ® 440GX AGPset 5.2.1 Clock Drivers Intel has supplied specifications to clock driver vendors, including the following. The specifications define requirements for Intel ® Pentium ® II processor-based systems with Intel ® 4...
Page 112 - Other Processor Components; Slot 1 Connector
Third-Party Vendor Information 5-4 Intel ® 440GX AGPset Design Guide 5.3 Other Processor Components 5.3.1 Slot 1 Connector Public information; see Intel ® Pentium ® II Processor Support Components Web page: http://developer.intel.com/design/PentiumII/components/index.htm 5.3.2 Mechanical Support Pub...
Page 118 - Power Connectors Front Panel Jumpers
Intel ® 440GX AGPset Platform Reference Design A-4 Intel ® 440GX AGPset Design Guide Power Connectors Front Panel Jumpers 32 This page shows the system ATX power connector, hardware reset logic, and standard chassis connectors for the hard disk, power LEDs, and speaker output. Included on this page ...
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