Intel 440GX - Manual

Intel 440GX

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Table of Contents:

  • Page 3 – Contents
  • Page 7 – Figures
  • Page 8 – Tables
  • Page 9 – Revision History
  • Page 11 – Introduction
  • Page 13 – About This Design Guide
  • Page 14 – References
  • Page 16 – Pentium
  • Page 17 – System Bus Interface
  • Page 18 – PCI Interface
  • Page 20 – Power Management; Design Recommendations; Voltage Definitions
  • Page 21 – General Design Recommendations
  • Page 23 – Motherboard Design
  • Page 25 – Motherboard Layout and Routing Guidelines; BGA Quadrant Assignment
  • Page 26 – Figure 2-2. Example ATX Placement for a UP Pentium
  • Page 27 – Board Description; Figure 2-3. Example NLX Placement for a UP Intel
  • Page 29 – Routing Guidelines
  • Page 30 – GTL+ Layout Recommendations; Single Processor Design; Single Processor Network Topology and Conditions; Figure 2-7. Recommended Topology for Single Processor Design
  • Page 31 – Single Processor Recommended Trace Lengths; Table 2-1. Recommended Trace Lengths for Single Processor Design
  • Page 32 – Dual Processor Systems; Dual Processor Network Topology and Conditions; Set Network Topology and Conditions; Figure 2-9. Recommended Topology for Dual Processor Design; Table 2-2. Recommended Trace Lengths for Dual Processor Designs
  • Page 33 – SET Trace Length Requirements
  • Page 34 – Additional Guidelines; Minimizing Crosstalk
  • Page 35 – Design Methodology
  • Page 36 – Performance Requirements
  • Page 37 – Topology Definition; Table 2-4. Recommended 100 MHz System Flight Time Specs
  • Page 38 – Post-Layout Simulation
  • Page 39 – Crosstalk and the Multi-Bit Adjustment Factor; Validation; Flight Time Measurement
  • Page 40 – Signal Quality Measurement; Table 2-6. Ringback Guidelines at the Intel
  • Page 41 – Timing Analysis
  • Page 42 – Table 2-10. Recommended 100 MHz System Timing Parameters; Table 2-11. Recommended 100 MHz System Flight Time Specs
  • Page 43 – AGP Layout and Routing Guidelines; AGP Connector (“Up Option) Layout Guidelines; Figure 2-14. AGP Connector Layout Guidelines
  • Page 44 – Table 2-13. Source Synchronous Motherboard Recommendations
  • Page 45 – Table 2-15. Source Synchronous Motherboard Recommendations
  • Page 47 – Matching the Reference Planes; Figure 2-17. Registered SDRAM DIMM Example
  • Page 48 – Trace Width vs. Trace Spacing; Memory Layout & Routing Guidelines
  • Page 54 – PCI Bus Routing Guidelines
  • Page 55 – Decoupling Guidelines: Intel; H o s t B r i d g e
  • Page 56 – Clock Routing Spacing; System Bus Clock Layout; Figure 2-30. Clock Trace Spacing Guidelines
  • Page 57 – PCI Clock Layout
  • Page 58 – AGP Clock Layout
  • Page 59 – Design Checklist
  • Page 61 – Overview
  • Page 67 – Slot 1 Decoupling Capacitors
  • Page 69 – CKBF - SDRAM 1 to 18 Clock Buffer; GCKE and DCLKWR Connection
  • Page 74 – SDRAM Connections
  • Page 75 – DIMM Solution With FET Switches; Registered SDRAM; Figure 3-3. Current Solution With Existing FET Switches; F E T
  • Page 76 – PIIX4E Connections
  • Page 80 – IDE Routing Guidelines; Cabling; Motherboard
  • Page 81 – P I I X 4 E
  • Page 82 – PIIX4E Power And Ground Pins; PCI Bus Signals
  • Page 83 – ISA Signals
  • Page 84 – USB Interface
  • Page 85 – Flash Design; Dual-Footprint Flash Design
  • Page 86 – Figure 3-6. nterfacing Intel’s Flash with PIIX4E in Desktop; P I I X 4
  • Page 88 – System and Test Signals; Figure 3-7. Interfacing Intel’s Flash with PIIX4E in Desktop
  • Page 90 – Power Button Implementation
  • Page 91 – Miscellaneous
  • Page 93 – Manageability Devices; LM79 Microprocessor System Hardware Monitor
  • Page 95 – USB and Multi-processor BIOS
  • Page 96 – Thermals / Cooling Solutions; Design Considerations; Mechanicals
  • Page 97 – Electricals
  • Page 98 – Layout Checklist; Routing and Board Fabrication; Applications and Add-in Hardware; Design Consideration
  • Page 101 – Debug Recommendations; Slot 1 Test Tools; Debug/Simulation Tools
  • Page 102 – FLO; THERM; Debug Features
  • Page 104 – Debug Logic Recommendations
  • Page 105 – Debug Considerations; Debug Layout; Debug Procedures
  • Page 107 – Third Party Vendors
  • Page 109 – Third-Party Vendor Information; Processors
  • Page 110 – Voltage Regulator Modules; Voltage Regulator Control Silicon; Table 5-5. Voltage Regulator Control Silicon Vendors
  • Page 111 – Clock Drivers; Power Management Components; Table 5-7. Power Management Component Vendors
  • Page 112 – Other Processor Components; Slot 1 Connector
  • Page 118 – Power Connectors Front Panel Jumpers
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Intel

®

440GX AGPset

Design Guide

March 1999

Order Number:

290651-001

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Summary

Page 3 - Contents

Intel ® 440GX AGPset Design Guide iii Contents 1 Introduction ................................................................................................................1-1 1.1 About This Design Guide ..............................................................................1-1 1.2 Referenc...

Page 7 - Figures

Intel ® 440GX AGPset Design Guide vii Figures 1-1 Intel ® Pentium ® II Processor / Intel ® 440GX AGPset System Block Diagram..................................................................................1-4 2-1 Major Signal Sections (82443GX Top View).................................................

Page 8 - Tables

viii Intel ® 440GX AGPset Design Guide Tables 2-1 Recommended Trace Lengths for Single Processor Design ........................ 2-7 2-2 Recommended Trace Lengths for Dual Processor Designs2 ....................... 2-8 2-3 SET Trace Length Requirements ..................................................

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