Intel 317698-001 - Manuals

82575 Ethernet Controller Design Guide 2 1.2 Reference Documents This application assumes that the designer is acquainted with high-speed design and board layout techniques. The following documents provide additional information: • 82575 Ethernet Controller Product Datasheet . Intel Corporation. • P...

3 82575 Ethernet Controller Design Guide 2.0 PCI Express Port Connection to the Device PCI Express (PCIe*) is a dual simplex point-to-point serial differential low-voltage interconnect. The signaling bit rate is 2.5 Gbps per lane per direction. Each port consists of a group of transmitters and recei...

82575 Ethernet Controller Design Guide 4 • If Maximum Link Width = x2, then the 82575 Ethernet Controller negotiates to either x2 or x1 • If Maximum Link Width = x1, then the 82575 Ethernet Controller only negotiates to x1 2.3.2 Polarity Inversion If polarity inversion is detected the Receiver must ...

5 82575 Ethernet Controller Design Guide Figure 1. Lane Reversal supported modes Configuration bits: EEPROM "Lane reversal disable" bit - disables lane reversal altogether 2.4 PCI Express Routing For information regarding the PCIe signal routing, please refer to the Intel PCIe Design Guide. ...

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7 82575 Ethernet Controller Design Guide 3.0 Ethernet Component Design Guidelines These sections provide recommendations for selecting components and connecting special pins. For 1000 BASE-T designs, the main design elements are the 82575 Gigabit Ethernet Controller, an integrated discrete or magnet...

82575 Ethernet Controller Design Guide 8 consistent from sample to sample and that measurements meet the published specifications. 3. Perform physical layer conformance testing and EMC (FCC and EN) testing in real systems. Vary temperature and voltage while performing system level tests. 3.1.2.2 Mod...

9 82575 Ethernet Controller Design Guide 3.2.1 LAN Disable for 82575 Ethernet Controller Gigabit Ethernet Controller The 82575 Ethernet Controller device has three signals that can be used for disabling Ethernet functions from system BIOS. LAN0_DIS_N and LAN1_DIS_N are the separated port disable sig...

82575 Ethernet Controller Design Guide 10 Table 2. Strapping Options for LAN Disable Table 3. Control Options for LAN Disable 3.2.2 Serial EEPROM The 82575 Ethernet Controller Gigabit Ethernet Controller uses an Serial Peripheral Interface (SPI)* EEPROM. Several words of the EEPROM are accessed auto...

11 82575 Ethernet Controller Design Guide • Legacy Wake On LAN (magic packets) is not supported• All the initializations normally loaded from the EEPROM will be loaded by the host driver. For more information, see the 82575 Gigabit Ethernet Controller Software Developer's Manual and the 82575 EEPROM...

82575 Ethernet Controller Design Guide 12 Table 5. 82575 Ethernet Controller EEPROM Memory Layout 3.2.3.1 EEUPDATE Intel has an MS-DOS* software utility called EEUPDATE, which can be used to program EEPROM images in development or production line environments. To obtain a copy of this program, conta...

13 82575 Ethernet Controller Design Guide 2. A particular address range of the IOADDR register defined by the IO Base Address Register (PCIe Control Register at offset 18h or 20h). 3. The Expansion ROM Base Address Register (PCIe Control Register at offset 30h). The 82575 controls accesses to the Fl...

82575 Ethernet Controller Design Guide 14 Note: Sector erase by SW is not supported. In order to delete a sector, the serial (bit bang) interface should be used. 3.2.4.3 FLASH Device Information While Intel does not make specific recommendations regarding FLASH devices, the following devices have be...

15 82575 Ethernet Controller Design Guide Figure 2. External BMC Connections with NC-SI and SMB The 82575 Ethernet Controller also supports the DMTF protocol. For more information about NC-SI and DMTF, see the 82575 Family System Management Application Note . 3.4 Power Supplies for the 82575 Etherne...

82575 Ethernet Controller Design Guide 16 Figure 3. Example Switching Voltage Regulator for 1.0 V and 1.8 V D N G G N I H C T I W S _ 0 V 1 C C V 3 V 3 C C V > > n o i t c e l e S r o t s i s e R r o t a l u g e R < < ) ) t f e l R + t h g i r R ( / p u R + 1 ( * 8 . 0 = t u o V ) t f e ...

17 82575 Ethernet Controller Design Guide The 1.8 V rail has a lower current requirement; however, the use of a SVR is still recommended for adequate margin. Using an LVR in this application is acceptable as long as adequate margin exists in the design, and sequencing can be controlled. Figure 3 sho...

82575 Ethernet Controller Design Guide 18 Figure 5. Proper power sequencing for 82575 Ethernet Controller Figure 6. Power On Flowchart In addition, the following limitations exist: W Y Y YY Vcc power on LAN_PWR_GOOD reset Load EEPROM Initialize FW Configure MAC and PHY Initialize RMII link PE_RST_n ...

19 82575 Ethernet Controller Design Guide • 1.8 V must not exceed 3.3 V.• 1.0 V must not exceed 3.3 V.• 1.0 V must not exceed 1.8 V. The power supplies are all expected to ramp during a short power-up internal (approximately 20ms or better). Do not leave the device in a prolonged state were some, bu...

82575 Ethernet Controller Design Guide 20 logic input to the 82575 Ethernet Controller that denotes auxiliary power is available. If AUX_PWR is asserted, the 82575 Ethernet Controller device will advertise that it supports wake up from a D3cold state. The 82575 Ethernet Controller device supports bo...

21 82575 Ethernet Controller Design Guide Figure 8. PCIe Power Management Flow/State Diagram 3.4.4.2 82575 Ethernet Controller Power Management If DisableD3Cold=0, the 82575 uses the AUX_PWR indication that auxiliary power is available to the controller, and therefore advertises D3cold Wake Up suppo...

82575 Ethernet Controller Design Guide 22 3.5 82575 Ethernet Controller Device Test Capability The 82575 Ethernet Controller Gigabit Ethernet Controller contains a test access port (3.3 V only) conforming to the IEEE 1149.1a-1994 (JTAG) Boundary Scan specification. To use the test access port, conne...

23 82575 Ethernet Controller Design Guide 3.6.2 Smartspeed SmartSpeed is an enhancement to auto-negotiation that allows the PHY to react to network conditions that are preventing a 1000BASE-T link, such as cable problems. These problems may allow auto-negotiation to complete, but then inhibit comple...

82575 Ethernet Controller Design Guide 24 The table below summarizes link speed as function of power management state, link speed control, and gigabit speed enabling: 3.6.5 Link Energy Detect The PHY de-asserts the Link Energy Detect Bit (PHYREG 25.4) whenever energy is not detected on the link. Thi...

25 82575 Ethernet Controller Design Guide 3.6.7 Auto-Negotiation differences between PHY, SerDes and SGMII SGMII protocol includes an auto-negotiation process in order to establish the MAC - PHY connection. This auto-negotiation process is not dependent on the SRDS0/ 1_SIG_DET signal, as this signal...

82575 Ethernet Controller Design Guide 26 is complete, the driver must read the PHY registers to determine the resolved flow control behavior of the link and reflect these in the MAC register settings (CTRL.TFCE and CTRL.RFCE). Note: Once PHY Auto-negotiation is complete, the PHY will assert a link ...

27 82575 Ethernet Controller Design Guide • The 82575 will put the PHY in power down unless CONNSW.ASCLR_DIS is set. In such a case the host driver is responsible for the clearing of the AUTOSENSE_EN bit According to the result of the interrupt, the software can then decide to switch to the other co...

82575 Ethernet Controller Design Guide 28 Note that if the device is configured to provide a 50MHz NC-SI clock (via the NC-SI Output Clock EEPROM bit), then the NC-SI clock must be provided in Device Disable mode as well the device should not be disabled. Device Disable is initiated by asserting the...

29 82575 Ethernet Controller Design Guide Note: To avoid signal contention, all four pins are set as input pins until after EEPROM configuration has been loaded. In addition to all four pins being individually configurable as inputs or outputs, they may be configured for use as general-purpose inter...

82575 Ethernet Controller Design Guide 30 4.0 Frequency Control Device Design Considerations This section provides information regarding frequency control devices, including crystals and oscillators, for use with all Intel Ethernet controllers. Several suitable frequency control devices are availabl...

31 82575 Ethernet Controller Design Guide 4.1.3 Programmable Crystal Oscillators A programmable oscillator can be configured to operate at many frequencies. The device contains a crystal frequency reference and a phase lock loop (PLL) clock generator. The frequency multipliers and divisors are contr...

82575 Ethernet Controller Design Guide 32 5.0 Crystal Selection Parameters All crystals used with Intel Ethernet controllers are described as “AT-cut,” which refers to the angle at which the unit is sliced with respect to the long axis of the quartz stone. Table 4 lists crystals which have been used...

33 82575 Ethernet Controller Design Guide Note: Crystals also carry other specifications for storage temperature, shock resistance, and reflow solder conditions. Crystal vendors should be consulted early in the design cycle to discuss the application and its environmental requirements. 5.5 Calibrati...

82575 Ethernet Controller Design Guide 34 An allowance of 3 pF to 7 pF accounts for lumped stray capacitance. The calculated load capacitance is 16 pF with an estimated stray capacitance of about 5 pF. Individual stray capacitance components can be estimated and added. For example, surface mount pad...

35 82575 Ethernet Controller Design Guide Even with a perfect support circuit, most crystals will oscillate slightly higher or slightly lower than the exact center of the target frequency. Therefore, frequency measurements (which determine the correct value for C1 and C2) should be performed with an...

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37 82575 Ethernet Controller Design Guide 6.0 Oscillator Support The 82575 clock input circuit is optimized for use with an external crystal. However, an oscillator can also be used in place of the crystal with the proper design considerations: • The clock oscillator has an internal voltage regulato...

82575 Ethernet Controller Design Guide 38 A low capacitance, high impedance probe (C < 1 pF, R > 500 K Ω ) should be used for testing. Probing the parameters can affect the measurement of the clock amplitude and cause errors in the adjustment. A test should also be done after the probe has bee...

39 82575 Ethernet Controller Design Guide 7.0 Ethernet Component Layout Guidelines These sections provide recommendations for performing printed circuit board layouts. Good layout practices are essential to meet IEEE PHY conformance specifications and EMI regulatory requirements. 7.1 Layout Consider...

82575 Ethernet Controller Design Guide 40 Minimizing the amount of space needed for the Ethernet LAN interface is important because other interfaces will compete for physical space on a motherboard near the connector. The Ethernet LAN circuits need to be as close as possible to the connector. Figure...

41 82575 Ethernet Controller Design Guide Figure 13. Layout for Integrated Magnetics Figure 14. Layout for Discrete Magnetics Termination resistors placed within 250 mils of silicon TVS Diodes for improved CDE Protection GND plane cut for High POT isolation Termination resistors placed within 250 mi...

82575 Ethernet Controller Design Guide 42 7.1.2 Crystals and Oscillators Clock sources should not be placed near I/O ports or board edges. Radiation from these devices may be coupled into the I/O ports and radiate beyond the system chassis. Crystals should also be kept away from the Ethernet magneti...

43 82575 Ethernet Controller Design Guide Figure 15. Recommended Crystal Placement and Layout 7.1.3 Board Stack Up Recommendations Printed circuit boards for these designs typically have six, eight, or more layers. Although, the 82575 does not dictate the stackup, here is an example of a typical six...

82575 Ethernet Controller Design Guide 44 7.1.4 Differential Pair Trace Routing for 10/100/1000 Designs Trace routing considerations are important to minimize the effects of crosstalk and propagation delays on sections of the board where high-speed signals exist. Signal traces should be kept as shor...

45 82575 Ethernet Controller Design Guide 7.1.4.1 Signal Termination and Coupling The four differential pairs of each port are terminated with 49.9 Ω (1% tolerance) resistors, placed near the 82575 controller. One resistor connects to the MDI+ signal trace and another resistor connects to the MDI- s...

82575 Ethernet Controller Design Guide 46 7.1.6.1 Signal Detect Each port of the 82575 controller has a Signal Detect pin for connection to optical transceivers. For designs without optical transceivers, these signals can be left unconnected because they have internal pull-up resistors. Signal Detec...

47 82575 Ethernet Controller Design Guide • Isolate I/O signals from high-speed signals to minimize crosstalk, which can increase EMI emission and susceptibility to EMI from other signals. • Avoid routing high-speed LAN traces near other high-frequency signals associated with a video controller, cac...

82575 Ethernet Controller Design Guide 48 7.1.14 Thermal Design Considerations The 82575 Gigabit Ethernet Controller contains a thermal sensor that is accessible through the SMBus. Trip points can be set in the EEPROM for the device. IcePak* and FlowTherm* models are available for the 82575 Ethernet...

82575 Ethernet Controller Design Guide 50 8.0 Thermal Management Please see the 82575 Thermal Application Note, available on the Intel Developer site. 9.0 Reference Design Bill of Materials The bill of materials for Intel’s reference designs is available on the Intel Developer site. 10.0 Design and ...