Intel 317698-001 - Manual

Table of Contents:

• Page 3 – Contents; Introduction
• Page 5 – Revision History
• Page 7 – The Intel; Scope
• Page 8 – Reference Documents; Institute of Electrical and Electronics
• Page 9 – PCI Express Port Connection to the Device; PCI Express Reference Clock; Link Width Configuration
• Page 10 – either x2 or x1; Polarity Inversion; indication of lane polarity inversion.; Lane Reversal; The following lane reversal modes are supported (see Figure below):
• Page 11 – Lane Reversal supported modes; altogether; PCI Express Routing; Guide. Contact your Intel representative for information.; Lane Reversal in x4 mode
• Page 12 – This page left intentionally blank.
• Page 13 – Ethernet Component Design Guidelines; General Design Considerations for Ethernet Controllers; Clock Source; Magnetics Module Qualification Steps
• Page 14 – Modules for 1000 BASE-T Ethernet; following guidelines to verify specific electrical parameters:; Third-Party Magnetics Manufacturers; • Discrete terminators; Designing with the 82575/EB/ES Gigabit Ethernet
• Page 15 – LAN Disable for 82575 Ethernet Controller Gigabit Ethernet; and does not have this restriction.; PCI/LAN Function Index
• Page 16 – Strapping Options for LAN Disable; Serial EEPROM; Map Application Note.; General Regions; The EEPROM is divided into four regions based on the type of access:; EEPROM-less Operation; • Non-manageability mode only
• Page 17 – For more information, see the; listed in; EEPROM Map Information; SPI EEPROMs for 82575 Ethernet Controller Controller
• Page 18 – 2575 Ethernet Controller EEPROM Memory Layout; EEUPDATE; this program, contact your Intel representative.; FLASH; within the FLASH address mapping.
• Page 19 – issue retry accesses during this time.; Flash Write Control; control mechanism described earlier.
• Page 20 – FLASH Device Information; System Management Interface Guide
• Page 21 – External BMC Connections with NC-SI and SMB; The 82575 Ethernet Controller also supports the DMTF protocol.; Power Supplies for the 82575 Ethernet Controller; Vmain and 3.3 Vaux voltages is recommended.
• Page 22 – Example Switching Voltage Regulator for 1.0 V and 1.8 V
• Page 23 – Example of Linear Voltage Regulator for 1.8 V power rail; 2575 Ethernet Controller Power Sequencing
• Page 24 – Proper power sequencing for 82575 Ethernet Controller; In addition, the following limitations exist:
• Page 25 – Using Regulators With Enable Pins; 2575 Ethernet Controller Device Power Supply Filtering; Minimum Number of Bypass Capacitors per Power Rail.; 2575 Ethernet Controller Controller Power Management and
• Page 26 – supports wake up from a D3cold state.; Power Management; PCIe Power Management; Power Management State Diagram; Dr
• Page 27 – PCIe Power Management Flow/State Diagram; 2575 Ethernet Controller Power Management
• Page 28 – 2575 Ethernet Controller Device Test Capability; Controller device is available for use in your test environment.; PHY Functionality; This section describes various functions of the PHY.; Auto Cross-over for MDI and MDI-X resolution; automatic) configuration is still possible by special cable, etc.
• Page 29 – Smartspeed; Using SmartSpeed; Flow Control
• Page 30 – speed control, and gigabit speed enabling:; Link Energy Detect; This bit is valid only if auto-negotiation is enabled.; Polarity Correction
• Page 31 – Auto-Negotiation differences between PHY, SerDes and SGMII; The following shows the outcome of this auto-negotiation process:; Copper PHY Link Configuration; negotiated or the user desires to manually configure the link.
• Page 32 – consider the link to be up.
• Page 33 – state, and then beginning the process for changing the link mode.; Device Disable
• Page 34 – mode as well the device should not be disabled.; BIOS handling of Device Disable; functions are invisible)
• Page 35 – configuration has been loaded.
• Page 36 – Frequency Control Device Design Considerations; “Crystal; Frequency Control Component Types; discussion of each follows, listed in preferred order.; Quartz Crystal; configurations and tolerances.
• Page 37 – Programmable Crystal Oscillators; another PLL that locks onto the signal at the other end.; Ceramic Resonator; Intel Ethernet controllers, and therefore, should not be utilized.
• Page 38 – Crystal Selection Parameters; Controller Advance Information Datasheet; Vibrational Mode; the scope of this document.; Nominal Frequency; operation – 10 MHz and 20 MHz transmit clocks, for 10BASE-T operation.; Frequency Tolerance; Crystal Manufacturers and Part Numbers
• Page 39 – to discuss the application and its environmental requirements.; Calibration Mode; frequency is calibrated at the factory.; Internal Oscillator Circuit; Load Capacitance; The formula for crystal load capacitance is as follows:; = allowance for additional capacitance in pads, traces and the chip
• Page 40 – the PCIe Design Guide for more information.; Shunt Capacitance; and contacts. The shunt capacitance should equal a maximum of 7 pF.; Equivalent Series Resistance; the crystal starts up. Use crystals with an ESR value of 50; Drive Level; than circular AT quartz blanks.; Aging; crystals. Use crystals with a maximum of ±5 ppm per year aging.; Reference Crystal
• Page 41 – Reference Crystal Selection
• Page 42 – This page is intentionally left blank.
• Page 43 – Oscillator Support; imposes a maximum input clock amplitude of 1.2 V.; Oscillator Solution; of about; 2575 Clock Oscillator Specifications
• Page 44 – ) should be used for; Reference Oscillator Circuit
• Page 45 – Ethernet Component Layout Guidelines; EMI regulatory requirements.; Layout Considerations for 82575 Ethernet Controllers; performed at all three speeds.; Guidelines for Component Placement; Careful component placement can:
• Page 46 – General Placement Distances for 1000 BASE-T Designs; the magnetics module.
• Page 47 – Layout for Integrated Magnetics
• Page 48 – Crystals and Oscillators; prevent interference.; Crystal layout considerations; between the load capacitor and the controller.
• Page 49 – Recommended Crystal Placement and Layout; Board Stack Up Recommendations; layer board stackup:; Ethernet Controller
• Page 50 – suggestions to help optimize board performance:; Trace Routing; frequency noise currents.
• Page 51 – Signal Termination and Coupling; Signal Trace Geometry for 1000 BASE-T Designs
• Page 52 – Signal Detect; speed signal and does not require special layout.; Routing 1.8 V to the Magnetics Center Tap; studied using electronics modeling software.; Signal Isolation; Some rules to follow for signal isolation:
• Page 53 – Power and Ground Planes; signal return, will significantly reduce EMI radiation.; Traces for Decoupling Capacitors; sufficiently large in diameter to decrease series inductance.; Light Emitting Diodes for Designs Based on the 82575; desirable to attach filter capacitors.
• Page 54 – Thermal Design Considerations; Intel® 82575 Ethernet Controller Thermal Design; Physical Layer Conformance Testing
• Page 56 – Thermal Management; your Intel representative to obtain these documents.; Reference Schematics; are available on the Intel Developer site.; version for use with your design.