Page 2 - CeleronTM Processor Development Kit Manual
Celeron™ Processor Development Kit Manual Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale ...
Page 3 - Contents; About This Manual
Celeron™ Processor Development Kit Manual iii Contents 1 About This Manual .................................................................................................. 1-1 1.1 Content Overview ............................................................................................... 1-1 1...
Page 4 - Hardware Reference
iv Celeron™ Processor Development Kit Manual 3.2.19 Post Code Debugger ......................................................................... 3-6 3.2.20 Clock Generation............................................................................... 3-6 3.2.21 Interrupt Map ..........................
Page 5 - PLD Code Listing; Figures
Celeron™ Processor Development Kit Manual v 5.10.1 Console Redirection .......................................................................... 5-9 5.10.2 CE-Ready Windows CE Loader ......................................................5-10 5.10.3 Integrated BIOS Debugger ............................
Page 7 - Content Overview; The following notations may be used throughout this manual.; Variables
Celeron™ Processor Development Kit Manual 1-1 About This Manual 1 This manual tells you how to set up and use the evaluation board and processor assembly included in your Celeron™ Processor Development Kit. 1.1 Content Overview Chapter 1, “About This Manual” - This chapter contains a description of ...
Page 8 - Technical Support; Electronic Support Systems; Online Documents; Numbers
1-2 Celeron™ Processor Development Kit Manual About This Manual 1.3 Technical Support 1.3.1 Electronic Support Systems Intel’s site on the World Wide Web (http://www.intel.com/) provides up-to-date technical information and product support. This information is available 24 hours per day, 7 days per ...
Page 9 - Intel Product Forums; Complete information on Intel forums is available at:; Telephone Technical Support; Product Literature; Germany
Celeron™ Processor Development Kit Manual 1-3 About This Manual 1.3.1.2 Intel Product Forums Intel provides technical expertise through electronic messaging. With publicly accessible forums, you have all of the benefits of email technical support, with the added benefit of the option of viewing prev...
Page 10 - Related Documents
1-4 Celeron™ Processor Development Kit Manual About This Manual 1.5 Related Documents Table 1-1. Related Documents Document Title Order Number Intel ® Celeron™ Processor datasheet 243658 Intel ® Celeron™ Processor Specification Update 243748 P6 Family of Processors Hardware Developer’s Manual 244001...
Page 11 - Getting Started; Overview; Processor Assembly Features
Celeron™ Processor Development Kit Manual 2-1 Getting Started 2 This chapter identifies the Development Kit’s key components, features and specifications, and tells you how to set up the board for operation. 2.1 Overview The evaluation board consists of a baseboard and a processor assembly. • The pr...
Page 12 - Baseboard Features; Included Hardware
2-2 Celeron™ Processor Development Kit Manual Getting Started 2.1.2 Baseboard Features The baseboard has these features: • Flash system BIOS ROM — General Software system BIOS — In-circuit BIOS upgradability • Two SDRAM DIMM connectors • 32-Mbyte SDRAM DIMM included — 4 Mbyte x64, 3.3 V, 66 MHz with...
Page 13 - Software Key Features
Celeron™ Processor Development Kit Manual 2-3 Getting Started 2.3 Software Key Features The software in the kit was chosen to facilitate development of real-time applications based on the components used in the evaluation board. The software tools included in your kit are described in this section. ...
Page 14 - Before You Begin
2-4 Celeron™ Processor Development Kit Manual Getting Started 2.3.2 QNX Software Systems, Ltd. QNX Real Time Operating System for Intel Architecture. • Small memory footprint of the QNX operating system with microGUI • QNX microGUI is a full featured graphical user interface (GUI) and windowing syst...
Page 15 - Setting up the Evaluation Board; Figure 2-1. Evaluation Board Jumpers and Connectors
Celeron™ Processor Development Kit Manual 2-5 Getting Started 2.5 Setting up the Evaluation Board Once you have gathered the hardware described in the last section, follow the steps below to set up your evaluation board. This manual assumes you are familiar with basic concepts involved with installi...
Page 17 - Configuring the BIOS
Celeron™ Processor Development Kit Manual 2-7 Getting Started — You may have to make changes to the system BIOS to enable this hard disk. See Chapter 5, “BIOS Quick Reference” for more information. • Floppy drive: A floppy disk drive connected to the evaluation board is the most direct method for lo...
Page 19 - Theory of Operation; Block Diagram; Figure 3-1. Evaluation Board Block Diagram
Celeron™ Processor Development Kit Manual 3-1 Theory of Operation 3 3.1 Block Diagram Figure 3-1. Evaluation Board Block Diagram Celeron™ Processor Sensor PIIX4E DRAM Bus ITP Voltage Regulator 72 -Bit DI MM 72-B it DI M M USB SMC FDC37B78X SuperI/O* PS/2 Mouse Floppy Drive ISA Bus Boot Flash Thermal...
Page 20 - System Operation; Celeron
3-2 Celeron™ Processor Development Kit Manual Theory of Operation 3.2 System Operation The Celeron™ processor evaluation board is a full-featured system board and processor assembly. The processor assembly includes either a 366-MHz or a 433-MHz Celeron processor (based on the development kit purchas...
Page 21 - System Bus Interface; ITP
Celeron™ Processor Development Kit Manual 3-3 Theory of Operation 3.2.2.1 System Bus Interface The 82443BX supports a maximum of 4 Gbytes of memory address space from the processor perspective. The largest address size is 32 bits. The 82443BX provides bus control signals and address paths for transf...
Page 22 - ACPI Power Management support; DRAM
3-4 Celeron™ Processor Development Kit Manual Theory of Operation 3.2.4 82371EB PCI to ISA/IDE Xcelerator (PIIX4E) The 82443BX is designed to support the PIIX4E I/O bridge. The PIIX4E is a highly-integrated multifunctional component that supports the following: • PCI Revision 2.1 compliant PCI-to-IS...
Page 23 - Two 16-bit ISA connectors are provided on the evaluation board.
Celeron™ Processor Development Kit Manual 3-5 Theory of Operation 3.2.10 IDE Support The evaluation board supports both a primary and secondary IDE interface via two 40-pin IDE connectors. The connector labeled IDE1 is the primary interface. IDE2 is the secondary interface. 3.2.11 Floppy Disk Suppor...
Page 24 - Post Code Debugger; The CY2309 Zero Delay Buffer is not used by the evaluation board.; Interrupt Map
3-6 Celeron™ Processor Development Kit Manual Theory of Operation 3.2.19 Post Code Debugger The evaluation board has an on-board Post Code Debugger. Data from any program that does an I/O write to 0080H is latched and displayed on the two LEDs (U12 and U13). During BIOS startup, codes are posted to ...
Page 25 - Memory Map
Celeron™ Processor Development Kit Manual 3-7 Theory of Operation 3.2.22 Memory Map Table 3-2. Memory Map Address Range (Hex) Size Description 100000-8000000 127.25M Extended Memory E0000-FFFFF 128K BIOS C8000-DFFFF Available expansion BIOS area (Flash disk memory window) A0000-C7FFF Off-board video...
Page 27 - Processor Assembly; Thermal Management
Celeron™ Processor Development Kit Manual 4-1 Hardware Reference 4 This section provides reference information on the system design. Included in this section is connector pinout information, jumper settings, and other system design information. 4.1 Processor Assembly The processor assembly contains ...
Page 28 - ISA and PCI Expansion Slots
4-2 Celeron™ Processor Development Kit Manual Hardware Reference 4.3 ISA and PCI Expansion Slots The evaluation platform has three PCI expansion slots and two ISA slots. 4.4 PCI Device Mapping On the evaluation platform the PCI devices are mapped to PCI device numbers by connecting an address line t...
Page 29 - Connector Pinouts; ATX Power Connector
Celeron™ Processor Development Kit Manual 4-3 Hardware Reference 4.5 Connector Pinouts 4.5.1 ATX Power Connector Table 4-2 shows the signals assigned to the ATX style power connector. Table 4-2. Primary Power Connector (J11) Pin Name Function 1 3.3 V 3.3 V 2 3.3 V 3.3 V 3 GND Ground 4 +5V +5 V VCC 5...
Page 30 - ITP Debugger Connector; P0 is the bottom connector. P1 is on top.
4-4 Celeron™ Processor Development Kit Manual Hardware Reference 4.5.2 ITP Debugger Connector 4.5.3 Stacked USB P0 is the bottom connector. P1 is on top. Table 4-3. ITP Connector Pin Assignment (J2 on the Processor Assembly) Pin Signal Pin Signal 1 RESET# 16 PREQ0# 2 GND 17 GND 3 DBRESET# 18 PRDY0# ...
Page 31 - Mouse and Keyboard Connectors; The keyboard port is on top. The mouse port is on the bottom.; Parallel Port
Celeron™ Processor Development Kit Manual 4-5 Hardware Reference 4.5.4 Mouse and Keyboard Connectors The keyboard port is on top. The mouse port is on the bottom. 4.5.5 Parallel Port Table 4-5. Keyboard and Mouse Connector Pinouts (J1 on the Baseboard) Pin Signal Name 1 Data 2 No Connect 3 Ground 4 ...
Page 32 - Serial Ports; COM1 is the top connector. COM2 is the bottom connector.; IDE Connector
4-6 Celeron™ Processor Development Kit Manual Hardware Reference 4.5.6 Serial Ports COM1 is the top connector. COM2 is the bottom connector. 4.5.7 IDE Connector Table 4-7. Serial Port Connector Pinout (J4) Pin Signal Name 1 DCD 2 Serial In (SIN) 3 Serial Out (SOUT) 4 DTR 5 GND 6 DSR 7 RTS 8 CTS 9 RI...
Page 33 - Floppy Drive Connector
Celeron™ Processor Development Kit Manual 4-7 Hardware Reference 4.5.8 Floppy Drive Connector Table 4-9. Diskette Drive Header Connector (JP1) Pin Signal Name Pin Signal Name 1 Ground 2 FDHDIN 3 Ground 4 Reserved 5 Key 6 FDEDIN 7 Ground 8 Index 9 Ground 10 Motor Enable A# 11 Ground 12 Drive Select B...
Page 34 - PCI Slot Connector
4-8 Celeron™ Processor Development Kit Manual Hardware Reference 4.5.9 PCI Slot Connector Table 4-10. PCI Slots (J7, J8, J9) Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name A1 VCC B1 - 12V A32 AD16 B32 AD17 A2 + 12V B2 GND A33 3.3V B33 CBE2# A3 VCC B3 GND A34 FRAME# B34 GND A4 VCC B4...
Page 35 - ISA Slot Connector
Celeron™ Processor Development Kit Manual 4-9 Hardware Reference 4.5.10 ISA Slot Connector Table 4-11. ISA Slots (J5, J6) Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name A1 IOCHK# B1 GND A26 SA5 B26 DACK2# A2 SD7 B2 RSTSLOT A27 SA4 B27 TC A3 SD6 B3 VCC A28 SA3 B28 BALE A4 SD5 B4 IRQB...
Page 36 - AGP Connector
4-10 Celeron™ Processor Development Kit Manual Hardware Reference 4.6 AGP Connector Table 4-12. AGP Slot (J13) Pin# B A Pin# B A 1 OVRCNT# 12V 34 Vddq3.3 Vddq3.3 2 5.0V TYPEDET# 35 AD21 AD22 3 5.0V Reserved 36 AD19 AD20 4 USB+ USB- 37 GND GND 5 GND GND 38 AD17 AD18 6 INTB# INTA# 39 C/BE2# AD16 7 CLK...
Page 37 - Jumpers; Table 4-13 shows default Jumper settings.
Celeron™ Processor Development Kit Manual 4-11 Hardware Reference 4.7 Jumpers Table 4-13 shows default Jumper settings. 4.7.1 Enable Spread Spectrum Clocking (J14) This jumper is used to enable or disable spread spectrum clocking on the clock synthesizer. When this jumper is in, a 0.5% down spread w...
Page 38 - To clear the RAM perform the following steps:; Push Button Switches; S1 is non-functional and reserved for future use.
4-12 Celeron™ Processor Development Kit Manual Hardware Reference 4.7.4 Flash BIOS VPP Select (J21) This jumper controls the voltage presented to the flash BIOS VPP pin. The 2-3 position supplies 5 V and is the default for normal operation. This position inhibits programming or erasing the flash BIO...
Page 39 - In-Circuit BIOS Update; To reprogram the BIOS:
Celeron™ Processor Development Kit Manual 4-13 Hardware Reference 4.8 In-Circuit BIOS Update The BIOS can be upgraded in-circuit. BIOS updates may periodically be posted to Intel’s Developers’ site at http://www.intel.com/design/. To reprogram the BIOS: 1. Set Jumper J21 and Jumper J22 to the 1-2 po...
Page 41 - BIOS Quick Reference; This software is provided for; BIOS and Pre-Boot Features
Celeron™ Processor Development Kit Manual 5-1 BIOS Quick Reference 5 The Celeron processor evaluation board is licensed with a single copy of Embedded BIOS and Embedded DOS software from General Software, Inc. 1 This software is provided for demonstration purposes only and must be licensed directly ...
Page 43 - Setup Screen System; Basic CMOS Configuration Screen; Figure 5-2. Embedded BIOS Setup Screen Menu
Celeron™ Processor Development Kit Manual 5-3 BIOS Quick Reference 5.3 Setup Screen System The system is configured from within the Setup Screen System, which is a series of menus that can be invoked from POST by pressing the <DEL> key if the main keyboard is being used, or by pressing ^C if t...
Page 44 - Configuring Drive Assignments; Configuring Floppy Drive Types; Figure 5-3. Embedded BIOS Basic Setup Screen
5-4 Celeron™ Processor Development Kit Manual BIOS Quick Reference 5.3.2 Configuring Drive Assignments Embedded BIOS allows the user to map a different file system to each drive letter. The BIOS allows file systems for each floppy (Floppy0 and Floppy1), each IDE drive (Ide0, Ide1, Ide2, and Ide3), a...
Page 45 - Configuring IDE Drive Types; User
Celeron™ Processor Development Kit Manual 5-5 BIOS Quick Reference 5.3.3 Configuring IDE Drive Types If true IDE disk file systems (and not their emulators, such as ROM, RAM, or flash disks) are mapped to drive letters, then the IDE drives themselves must be configured in this section. The following...
Page 46 - Configuring Boot Actions; Debugger; No action POST proceeds to the next activity in the sequence.; Custom Configuration Setup Screen
5-6 Celeron™ Processor Development Kit Manual BIOS Quick Reference 5.4 Configuring Boot Actions Embedded BIOS supports up to six different user-defined steps in the boot sequence. When the entire system has been initialized, POST executes these steps in order until an operating system successfully l...
Page 47 - Shadow Configuration Setup Screen; Figure 5-4. Embedded BIOS Custom Setup Screen
Celeron™ Processor Development Kit Manual 5-7 BIOS Quick Reference 5.6 Shadow Configuration Setup Screen The system’s Shadow Configuration Setup Screen (Figure 5-5) allows the selective enabling and disabling of shadowing in 16 Kbyte sections, except for the top 64 Kbytes of the BIOS ROM, which is s...
Page 48 - Standard Diagnostics Routines Setup Screen; Figure 5-6. Standard Diagnostic Routines Setup Screen
5-8 Celeron™ Processor Development Kit Manual BIOS Quick Reference 5.7 Standard Diagnostics Routines Setup Screen Embedded systems may require automated burn-in testing in the development cycle. This facility is provided directly in the system’s system BIOS through the Standard Diagnostics Routines ...
Page 49 - Start RS232 Manufacturing Link Setup Screen; Console Redirection; Figure 5-7. Start RS232 Manufacturing Link Setup Screen
Celeron™ Processor Development Kit Manual 5-9 BIOS Quick Reference 5.9 Start RS232 Manufacturing Link Setup Screen The Embedded BIOS Manufacturing Mode may be invoked from the Setup Screen main menu, as well as a boot activity. Once invoked, Manufacturing Mode takes over the system and freezes the c...
Page 50 - CE-Ready Windows CE Loader
5-10 Celeron™ Processor Development Kit Manual BIOS Quick Reference The software on the target can be any terminal emulation program that supports ANSI terminal mode, using 9600 baud, no parity, and one stop bit (Note: This can be modified by the OEM during BIOS adaptation.) The program must be set ...
Page 52 - Embedded BIOS POST Codes
5-12 Celeron™ Processor Development Kit Manual BIOS Quick Reference A complete discussion of the debugger is beyond the scope of this chapter; however, complete documentation is available from General Software via the web at http://www.gensw.com. 5.11 Embedded BIOS POST Codes Embedded BIOS writes pr...
Page 55 - Embedded BIOS Beep Codes
Celeron™ Processor Development Kit Manual 5-15 BIOS Quick Reference 5.12 Embedded BIOS Beep Codes Embedded BIOS tests much of the system hardware early in POST before messages can be displayed on the screen. When system failures are encountered at these early stages, POST uses beep codes (a sequence...
Page 57 - The code listing below is for the 22V10 PLD.
Celeron™ Processor Development Kit Manual A-1 PLD Code Listing A The code listing below is for the 22V10 PLD. TITLE 22V10 PORT 80 ADDRESS DECODER / FLASH DECODE PATTERN 1 REVISION B AUTHOR CHRIS BANYAI COMPANY INTEL CORPORATION DATE 10/1/97 OPTIONS SECURITY = OFF ; ( part was 22V10FN before conversi...
Page 59 - Bill of Materials
Celeron™ Processor Development Kit Manual B-1 Bill of Materials B Table B-1 is the bill of materials for the baseboard. Table B-2 is the bill of materials for the Processor Assembly. Table B-1. Baseboard Bill of Materials (Sheet 1 of 4) Reference Description Manufacturer Manufacturer P/N Notes J14,J...
Page 65 - Schematics
Celeron™ Processor Development Kit Manual C-1 Schematics C The most current schematics, including “flat” schematics (without the 400-pin connector), are located on Intel’s Developer Web site at: http://www.intel.com/design/intarch/schems/. Schematics are provided for the following items: Baseboard: ...
Page 70 - Socket 0
A A B B C C D D E E 4 4 3 3 2 2 1 1 Slave address 10100000b Socket 0 THIS DRAWING CONTAINS INFORMATION WHICH HA S NOT BEEN VERIFIED FOR MANUFACTURING AS AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATIO N. {Doc} D DIMM0 C 5 22 Thursday, February 25, 1999 Title Size Docu...
Page 71 - Socket 1
A A B B C C D D E E 4 4 3 3 2 2 1 1 Slave address 10100001b Socket 1 THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AS AN END U SER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATIO N. {Doc} D DIMM1 C 6 22 Thursday, February 25, 1999 Title Size Docu...
Page 72 - Socket 2
A A B B C C D D E E 4 4 3 3 2 2 1 1 Slave address 10100010b Socket 2 Note: J16 is not popula ted THIS DRAWING CONTAINS INFORMATION WHICH HA S NOT BEEN VERIFIED FOR MANUFACTURING AS AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATIO N. {Doc} D DIMM2 C 7 22 Thursday, Febru...
Page 83 - ISA Slots
A A B B C C D D E E 4 4 3 3 2 2 1 1 ISA Slots J5/J6 V5_ 0: B03, B29, B3 1, D16 J5/J6 GN D: B01, B10, D18 J5/J6: +12V B09 -12V B07 -5V B05 Note Cap Direc tion Note Cap Direc tion THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AS AN END U SER PRODUCT. INTEL IS NOT RESP...
Page 88 - Revision A1; Celeron(TM) Processor in PPGA Daughter Board
5 5 4 4 3 3 2 2 1 1 D D C C B B A A No license, express or implied, by estoppel or otherwise, to a n y intellectual property rights is granted here i n . Revision A1 THIS DRAWING CONTAINS INFOR MATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACT URING AS AN END USER PRODUCT. INTEL IS NOT R ESPONSIBLE FO...
Page 99 - Index
Celeron™ Processor Development Kit Manual Index-1 Index #, defined 1-1 440BX AGPset 3-2 82371EB PCI ISA IDE Xcelerator (PIIX4E) 2-1 , 3-4 82443BX Host Bridge/Controller 2-1 A Address size 3-3 AGP connector 3-5 , 4-10 AGP support 2-1 , 3-2 , 3-3 ATX power connector 4-3 B Baseboard 2-1 Beep codes 5-1 ...
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