Intel 273246-002 - Manual

Intel 273246-002

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Table of Contents:

  • Page 2 – CeleronTM Processor Development Kit Manual
  • Page 3 – Contents; About This Manual
  • Page 4 – Hardware Reference
  • Page 5 – PLD Code Listing; Figures
  • Page 7 – Content Overview; The following notations may be used throughout this manual.; Variables
  • Page 8 – Technical Support; Electronic Support Systems; Online Documents; Numbers
  • Page 9 – Intel Product Forums; Complete information on Intel forums is available at:; Telephone Technical Support; Product Literature; Germany
  • Page 10 – Related Documents
  • Page 11 – Getting Started; Overview; Processor Assembly Features
  • Page 12 – Baseboard Features; Included Hardware
  • Page 13 – Software Key Features
  • Page 14 – Before You Begin
  • Page 15 – Setting up the Evaluation Board; Figure 2-1. Evaluation Board Jumpers and Connectors
  • Page 17 – Configuring the BIOS
  • Page 19 – Theory of Operation; Block Diagram; Figure 3-1. Evaluation Board Block Diagram
  • Page 20 – System Operation; Celeron
  • Page 21 – System Bus Interface; ITP
  • Page 22 – ACPI Power Management support; DRAM
  • Page 23 – Two 16-bit ISA connectors are provided on the evaluation board.
  • Page 24 – Post Code Debugger; The CY2309 Zero Delay Buffer is not used by the evaluation board.; Interrupt Map
  • Page 25 – Memory Map
  • Page 27 – Processor Assembly; Thermal Management
  • Page 28 – ISA and PCI Expansion Slots
  • Page 29 – Connector Pinouts; ATX Power Connector
  • Page 30 – ITP Debugger Connector; P0 is the bottom connector. P1 is on top.
  • Page 31 – Mouse and Keyboard Connectors; The keyboard port is on top. The mouse port is on the bottom.; Parallel Port
  • Page 32 – Serial Ports; COM1 is the top connector. COM2 is the bottom connector.; IDE Connector
  • Page 33 – Floppy Drive Connector
  • Page 34 – PCI Slot Connector
  • Page 35 – ISA Slot Connector
  • Page 36 – AGP Connector
  • Page 37 – Jumpers; Table 4-13 shows default Jumper settings.
  • Page 38 – To clear the RAM perform the following steps:; Push Button Switches; S1 is non-functional and reserved for future use.
  • Page 39 – In-Circuit BIOS Update; To reprogram the BIOS:
  • Page 41 – BIOS Quick Reference; This software is provided for; BIOS and Pre-Boot Features
  • Page 43 – Setup Screen System; Basic CMOS Configuration Screen; Figure 5-2. Embedded BIOS Setup Screen Menu
  • Page 44 – Configuring Drive Assignments; Configuring Floppy Drive Types; Figure 5-3. Embedded BIOS Basic Setup Screen
  • Page 45 – Configuring IDE Drive Types; User
  • Page 46 – Configuring Boot Actions; Debugger; No action POST proceeds to the next activity in the sequence.; Custom Configuration Setup Screen
  • Page 47 – Shadow Configuration Setup Screen; Figure 5-4. Embedded BIOS Custom Setup Screen
  • Page 48 – Standard Diagnostics Routines Setup Screen; Figure 5-6. Standard Diagnostic Routines Setup Screen
  • Page 49 – Start RS232 Manufacturing Link Setup Screen; Console Redirection; Figure 5-7. Start RS232 Manufacturing Link Setup Screen
  • Page 50 – CE-Ready Windows CE Loader
  • Page 52 – Embedded BIOS POST Codes
  • Page 55 – Embedded BIOS Beep Codes
  • Page 57 – The code listing below is for the 22V10 PLD.
  • Page 59 – Bill of Materials
  • Page 65 – Schematics
  • Page 70 – Socket 0
  • Page 71 – Socket 1
  • Page 72 – Socket 2
  • Page 83 – ISA Slots
  • Page 88 – Revision A1; Celeron(TM) Processor in PPGA Daughter Board
  • Page 99 – Index
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Celeron™ Processor

Development Kit Manual

July 1999

Order Number: 273246-002

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Summary

Page 2 - CeleronTM Processor Development Kit Manual

Celeron™ Processor Development Kit Manual Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale ...

Page 3 - Contents; About This Manual

Celeron™ Processor Development Kit Manual iii Contents 1 About This Manual .................................................................................................. 1-1 1.1 Content Overview ............................................................................................... 1-1 1...

Page 4 - Hardware Reference

iv Celeron™ Processor Development Kit Manual 3.2.19 Post Code Debugger ......................................................................... 3-6 3.2.20 Clock Generation............................................................................... 3-6 3.2.21 Interrupt Map ..........................

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