Analog Devices ADSP-2181 - Manuals

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Manual

Manual Analog Devices ADSP-2181

Summary

Page 5 - Table I. Interrupt Priority & Interrupt Vector Addresses; Interrupt Vector; IRQE

ADSP-2181/ADSP-2183 REV. 0 – 5 – Table I. Interrupt Priority & Interrupt Vector Addresses Interrupt Vector Source of Interrupt Address (Hex) Reset (or Power-Up with PUCR = 1) 0000 (Highest Priority) Power Down (Nonmaskable) 002C IRQ2 0004 IRQL1 0008 IRQL0 000C SPORT0 Transmit 0010 SPORT0 Receive...

Page 6 - Figure 3. External Crystal Connections; Reset

ADSP-2181/ADSP-2183 REV. 0 – 6 – When the IDLE (n) instruction is used, it effectively slows downthe processor’s internal clock and thus its response time to in-coming interrupts. The one-cycle response time of the standardidle state is increased by n, the clock divisor. When an enabledinterrupt is ...

Page 7 - PMOVLAY Memory; INTERNAL 8K; Data Memory; Figure 6. Data Memory; Memory Architecture; K INTERNAL

ADSP-2181/ADSP-2183 REV. 0 – 7 – Table II. PMOVLAY Memory A13 A12:0 0 Internal Not Applicable Not Applicable 1 External 0 13 LSBs of Address Overlay 1 Between 0x2000and 0x3FFF 2 External 1 13 LSBs of Address Overlay 2 Between 0x2000and 0x3FFF This organization provides for two external 8K overlay se...

Page 9 - Table VI. Boot Summary Table; MMAP; Bus Request & Bus Grant; BDMA Booting

ADSP-2181/ADSP-2183 REV. 0 – 9 – Table VI. Boot Summary Table MMAP BMODE Booting Method 0 0 BDMA feature is used in default modeto load the first 32 program memorywords from the byte memory space.Program execution is held off until all32 words have been loaded. 0 1 IDMA feature is used to load any i...

Page 10 - Description: The I/O space read and write instructions move

ADSP-2181/ADSP-2183 REV. 0 – 1 0 – If the ADSP-2181/ADSP-2183 is performing an externalmemory access when the external device asserts the BR signal, then it will not three-state the memory interfaces or assert the BG signal until the processor cycle after the access completes. The instruction does n...

Page 11 - Target Board Connector for EZ-ICE Probe; GND; Figure 7. Target Board Connector for EZ-ICE; Target Memory Interface

ADSP-2181/ADSP-2183 REV. 0 – 1 1 – These ADSP-2181/ADSP-2183 pins must be connected only tothe EZ-ICE connector in the target system. These pins have nofunction except during emulation, and do not require pull-up orpull-down resistors. The traces for these signals between theADSP-2181/ADSP-2183 and ...

Page 13 - ESD SENSITIVITY; ADSP-2181 TIMING PARAMETERS; GENERAL NOTES

ADSP-2181/ADSP-2183 REV. 0 – 1 3 – ESD SENSITIVITY The ADSP-2181 is an ESD (electrostatic discharge) sensitive device. Electrostatic charges readilyaccumulate on the human body and equipment and can discharge without detection. Permanentdamage may occur to devices subjected to high energy electrosta...

Page 14 - ENVIRONMENTAL CONDITIONS; Package; POWER DISSIPATION; Total Power Dissipation = P; = internal power dissipation from Power vs. Frequency; Pins; DMS; n MODES

ADSP-2181/ADSP-2183 REV. 0 – 1 4 – ADSP-2181 ENVIRONMENTAL CONDITIONS Ambient Temperature Rating: T AMB = T CASE – (PD × θ C A ) T CASE = Case Temperature in ° C PD = Power Dissipation in W θ CA = Thermal Resistance (Case-to-Ambient) θ J A = Thermal Resistance (Junction-to-Ambient) θ J C = Thermal R...

Page 15 - from which; Output Enable Time; ) is the interval from when; (at Maximum Ambient Operating Temperature); (at Maximum Ambient Operating; ) is the difference of t; and t

ADSP-2181/ADSP-2183 REV. 0 – 1 5 – t DECAY , is dependent on the capacitive load, C L , and the current load, i L , on the output pin. It can be approximated by the fol- lowing equation: t DECAY = C L • 0. 5 V i L from which t DIS = t MEASURED – t DECAY is calculated. If multiple pins (such as the d...

Page 17 - ADSP-2183 TIMING PARAMETERS

ADSP-2181/ADSP-2183 REV. 0 – 1 7 – MEMORY TIMING SPECIFICATIONS The table below shows common memory device specificationsand the corresponding ADSP-2183 timing parameters, for yourconvenience. Memory ADSP-2183 Timing Device Timing Parameter Specification Parameter Definition Address Setup to t ASW A...

Page 19 - CAPACITIVE LOADING

ADSP-2181/ADSP-2183 REV. 0 – 1 9 – ADSP-2183 CAPACITIVE LOADING Figures 17 and 18 show the capacitive loading characteristics ofthe ADSP-2183. C L – pF RISE TIME (0.4V – 2.4V) – ns 30 0 0 200 25 50 75 100 125 150 175 25 20 15 10 5 T = +85 ° C V DD = 3.0V Figure 17. Typical Output Rise Time vs. Load ...

Page 20 - NOTE; Figure 22. Clock Signals

ADSP-2181/ADSP-2183 REV. 0 – 2 0 – ADSP-2181 Parameter Min Max Unit Clock Signals and Reset Timing Requirements: t CKI CLKIN Period 60 150 ns t CKIL CLKIN Width Low 20 ns t CKIH CLKIN Width High 20 ns Switching Characteristics: t CKL CLKOUT Width Low 0.5t CK – 7 ns t CKH CLKOUT Width High 0.5t CK – ...

Page 21 - NOTES; IRQx; Figure 23. Interrupts and Flags

ADSP-2181/ADSP-2183 REV. 0 – 2 1 – ADSP-2181 Parameter Min Max Unit Interrupts and Flag Timing Requirements: t IFS IRQx , FI, or PFx Setup before CLKOUT Low 1, 2, 3, 4 0.25t CK + 15 ns t IFH IRQx , FI, or PFx Hold after CLKOUT High 1, 2, 3, 4 0.25t CK ns Switching Characteristics:t FOH Flag Output H...

Page 22 - Figure 24. Bus Request–Bus Grant

ADSP-2181/ADSP-2183 REV. 0 – 2 2 – ADSP-2181/ADSP-2183 Parameter Min Max Unit Bus Request/Grant Timing Requirements: t BH BR Hold after CLKOUT High 1 0.25t CK + 2 ns t BS BR Setup before CLKOUT Low 1 0.25t CK + 17 ns Switching Characteristics:t SD CLKOUT High to xMS , 0.25t CK + 10 ns RD , WR Disabl...

Page 23 - Figure 25. Memory Read

ADSP-2181/ADSP-2183 REV. 0 – 2 3 – ADSP-2181 Parameter Min Max Unit Memory Read Timing Requirements:t RDD RD Low to Data Valid 0.5t CK – 9 + w ns t AA A0-A13, xMS to Data Valid 0.75t CK – 10.5 + w ns t RDH Data Hold from RD High 0 ns Switching Characteristics:t RP RD Pulse Width 0.5t CK – 5 + w ns t...

Page 24 - Figure 26. Memory Write

ADSP-2181/ADSP-2183 REV. 0 – 2 4 – ADSP-2181/ADSP-2183 Parameter Min Max Unit Memory Write Switching Characteristics:t DW Data Setup before WR High 0.5t CK – 7+ w ns t DH Data Hold after WR High 0.25t CK – 2 ns t WP WR Pulse Width 0.5t CK – 5 + w ns t WDE WR Low to Data Enabled 0 ns t ASW A0-A13, xM...

Page 25 - Figure 27. Serial Ports

ADSP-2181/ADSP-2183 REV. 0 – 2 5 – ADSP-2181/ADSP-2183 Parameter Min Max Unit Serial Ports Timing Requirements:t SCK SCLK Period 50 ns t SCS DR/TFS/RFS Setup before SCLK Low 4 ns t SCH DR/TFS/RFS Hold after SCLK Low 7 ns t SCP SCLK IN Width 20 ns Switching Characteristics:t CC CLKOUT High to SCLK OU...

Page 26 - IACK; IS; Figure 28. IDMA Address Latch

ADSP-2181/ADSP-2183 REV. 0 – 2 6 – ADSP-2181/ADSP-2183 Parameter Min Max Unit IDMA Address Latch Timing Requirements:t IALP Duration of Address Latch 1, 3 10 ns t IASU IAD15–0 Address Setup before Address Latch End 3 5 ns t IAH IAD15–0 Address Hold after Address Latch End 3 2 ns t IKA IACK Low befor...

Page 31 - 28-Lead TQFP Package Pinout

ADSP-2181/ADSP-2183 REV. 0 – 3 1 – 128-Lead TQFP Package Pinout 65 64 102 IRQL1 TFS1/IRQ1 RFS1/IRQ0 103 1 128 39 38 BGEBGBREBR IS V DD GNDD23 IRD IWR GND D22D21D20 D18 D19 D17D16D15 V DD GND D14D13D12D11 D9D8D7D6D5 D10 GND D2D1D0 D4D3 V DD GND PF4 PF5 PF6 PF7 IAD0 IAD1 IAD2 IAD3 IAD4 IAD5 GND IAD6 I...

Page 32 - TQFP Pin Configurations

ADSP-2181/ADSP-2183 REV. 0 – 3 2 – TQFP Pin Configurations TQFP Pin TQFP Pin TQFP Pin TQFP Pin Number Name Number Name Number Name Number Name 1 IAL 33 A12 65 ECLK 97 D19 2 PF3 34 A13 66 ELOUT 98 D20 3 PF2 35 IRQE 67 ELIN 99 D21 4 PF1 36 MMAP 68 EINT 100 D22 5 PF0 37 PWD 69 EBR 101 D23 6 WR 38 IRQ2 ...

Page 33 - OUTLINE DIMENSIONS

ADSP-2181/ADSP-2183 REV. 0 – 3 3 – OUTLINE DIMENSIONS 128-Lead Metric Thin Plastic Quad Flatpack (TQFP) 65 64 102 103 1 128 39 38 E 3 E 1 E B e D 3 D 1 D TOP VIEW (PINS DOWN) SEATING PLANE L A D A 1 A 2 MILLIMETERS INCHES SYMBOL MIN TYP MAX MIN TYP MAX A 1.60 0.063 A 1 0.05 0.15 0.002 0.006 A 2 1.30...

Page 34 - 28-Lead PQFP Package Pinout

ADSP-2181/ADSP-2183 REV. 0 – 3 4 – 128-Lead PQFP Package Pinout 65 64 96 97 1 33 32 TOP VIEW (PINS DOWN) 128L PQFP (28mm x 28mm) 128 PF1 PF2 PF3 IAL BGEBGBREBR IS V DD GND D23 IRD IWR GND D22D21D20 D18 D19 D17D16D15 V DD GNDD14D13D12D11 D9D8D7D6D5GND D2D1D0 D10 D4D3 V DD GND PF4 PF5 PF6 PF7 IAD0 IAD...

Page 35 - PQFP Pin Configurations

ADSP-2181/ADSP-2183 REV. 0 – 3 5 – PQFP Pin Configurations PQFP Pin PQFP Pin PQFP Pin PQFP Pin Number Name Number Name Number Name Number Name 1 PF0 33 PWD 65 EBR 97 D23 2 WR 34 IRQ2 66 BR 98 GND 3 RD 35 BMODE 67 EBG 99 IWR 4 IOMS 36 PWDACK 68 BG 100 IRD 5 BMS 37 IACK 69 VDD 101 IAD15 6 DMS 38 BGH 7...

Page 37 - ORDERING GUIDE

ADSP-2181/ADSP-2183 REV. 0 – 3 7 – ORDERING GUIDE Ambient Instruction Temperature Rate Package Package Part Number Range (MHz) Description Option* ADSP-2181KST-115 0 ° C to +70 ° C 28.8 128-Lead TQFP ST-128 ADSP-2181BST-115 –40 ° C to +85 ° C 28.8 128-Lead TQFP ST-128 ADSP-2181KS-115 0 ° C to +70 ° ...