Analog Devices ADSP-2186 - Manual
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Table of Contents:
- Page 2 – Figure 1. Block Diagram
- Page 4 – NOTES
- Page 5 – Source Of Interrupt; IRQE
- Page 6 – Figure 2. Basic System Configuration
- Page 7 – Clock Signals; DSP; Figure 3. External Crystal Connections; Reset; MEMORY ARCHITECTURE; EXTERNAL 8K
- Page 8 – RESERVED; Data Memory; Figure 6. Data Memory; DMOVLAY Memory; Composite Memory Select (
- Page 9 – Byte Memory; Internal; IS
- Page 10 – MODE C MODE B MODE A Booting Method; IDMA Port Booting
- Page 12 – Target Board Connector for EZ-ICE; GND; Figure 7. Target Board Connector for EZ-ICE; Target Memory Interface
- Page 13 – Guaranteed but not tested.; Applies to TQFP package type.
- Page 14 – ABSOLUTE MAXIMUM RATINGS*; ADSP-2186 TIMING PARAMETERS; GENERAL NOTES; MEMORY TIMING SPECIFICATIONS; xMS
- Page 15 – ENVIRONMENTAL CONDITIONS; Package; POWER DISSIPATION; Example; DMS; n MODES
- Page 16 – CAPACITIVE LOADING; (at Maximum Ambient Operating Temperature); (at Maximum Ambient Operating; ) is the difference of t; from which
- Page 17 – TIMING PARAMETERS; RESET; Figure 14. Clock Signals
- Page 18 – Parameter; and t; IRQx; Figure 15. Interrupts and Flags
- Page 19 – Figure 16. Bus Request–Bus Grant
- Page 20 – Figure 17. Memory Read
- Page 21 – Figure 18. Memory Write
- Page 22 – Figure 19. Serial Ports
- Page 23 – IACK; Figure 20. IDMA Address Latch
- Page 28 – 00-Lead TQFP Package Pinout
- Page 29 – TQFP Pin Configurations; EINT
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
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ADSP-2186
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1997
DSP Microcomputer
FUNCTIONAL BLOCK DIAGRAM
SERIAL PORTS
SPORT 1
SPORT 0
MEMORY
PROGRAMMABLE
I/O
AND
FLAGS
BYTE DMA
CONTROLLER
8K 24
PROGRAM
MEMORY
8K 16
DATA
MEMORY
TIMER
ADSP-2100 BASE
ARCHITECTURE
SHIFTER
MAC
ALU
ARITHMETIC UNITS
POWER-DOWN
CONTROL
PROGRAM
SEQUENCER
DAG 2
DAG 1
DATA ADDRESS
GENERATORS
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
EXTERNAL
DATA
BUS
EXTERNAL
ADDRESS
BUS
INTERNAL
DMA
PORT
EXTERNAL
DATA
BUS
OR
FULL MEMORY
MODE
HOST MODE
FEATURES
PERFORMANCE
30 ns Instruction Cycle Time 33 MIPS Sustained
Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in
Every Instruction Cycle
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby
Power Dissipation with 100 Cycle Recovery from
Power-Down Condition
Low Power Dissipation in Idle Mode
INTEGRATION
ADSP-2100 Family Code Compatible, with Instruction
Set Extensions
40K Bytes of On-Chip RAM, Configured as
8K Words On-Chip Program Memory RAM and
8K Words On-Chip Data Memory RAM
Dual Purpose Program Memory for Both Instruction
and Data Storage
Independent ALU, Multiplier/Accumulator and Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides
Zero Overhead Looping Conditional Instruction
Execution
Programmable 16-Bit Interval Timer with Prescaler
100-Lead TQFP
SYSTEM INTERFACE
16-Bit Internal DMA Port for High Speed Access to
On-Chip Memory (Mode Selectable)
4 MByte Byte Memory Interface for Storage of Data
Tables & Program Overlays
8-Bit DMA to Byte Memory for Transparent Program
and Data Memory Transfers (Mode Selectable)
I/O Memory Interface with 2048 Locations Supports
Parallel Peripherals (Mode Selectable)
Programmable Memory Strobe and Separate I/O Memory
Space Permits “Glueless” System Design
(Mode Selectable)
Programmable Wait State Generation
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory, e.g., EPROM, or
Through Internal DMA Port
Six External Interrupts
13 Programmable Flag Pins Provide Flexible System
Signaling
UART Emulation through Software SPORT Reconfiguration
ICE-Port™* Emulator Interface Supports Debugging
in Final Systems
GENERAL NOTE
This data sheet represents production grade specifications for
the ADSP-2186 (5 V) processor. This data sheet also contains
preliminary (x-grade) specifications for the new ADSP-2186
40 MHz processor.
GENERAL DESCRIPTION
The ADSP-2186 is a single-chip microcomputer optimized for
digital signal processing (DSP) and other high speed numeric
processing applications.
The ADSP-2186 combines the ADSP-2100 family base archi-
tecture (three computational units, data address generators and
a program sequencer) with two serial ports, a 16-bit internal
DMA port, a byte DMA port, a programmable timer, Flag I/O,
extensive interrupt capabilities and on-chip program and data
memory.
The ADSP-2186 integrates 40K bytes of on-chip memory con-
figured as 8K words (24-bit) of program RAM and 8K words
(16-bit) of data RAM. Power-down circuitry is also provided to
meet the low power needs of battery operated portable equip-
ment. The ADSP-2186 is available in 100-pin TQFP package.
In addition, the ADSP-2186 supports new instructions, which
include bit manipulations—bit set, bit clear, bit toggle, bit test—
new ALU constants, new multiplication instruction (x squared),
*ICE-Port is a trademark of Analog Devices, Inc.
All trademarks are the property of their respective holders.
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Summary
ADSP-2186 – 2 – REV. 0 biased rounding, result free ALU operations, I/O memory trans-fers and global interrupt masking for increased flexibility. Fabricated in a high speed, double metal, low power, CMOSprocess, the ADSP-2186 operates with a 30 ns instruction cycletime. Every instruction can execute...
ADSP-2186 – 4 – REV. 0 concurrently on multiplexed pins. In cases where pin func-tionality is reconfigurable, the default state is shown in plaintext; alternate functionality is shown in italics. Common-Mode Pins # Input/ Pin of Out- Name(s) Pins put Function RESET 1 I Processor Reset Input BR 1 I B...
ADSP-2186 – 5 – REV. 0 To minimize power consumption during power-down, configurethe programmable flag as an output when connected to a three-stated buffer. This ensures that the pin will be held at a constantlevel and not oscillate should the three-state driver’s level hoveraround the logic switchi...
