Page 3 - Contents; Section; Introduction
Contents iii July 2005 SLES140 Contents Section Page 1 Introduction 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Detailed Functionality 2 . . . . . . . . . . . . . . . . . . . . . . . . ....
Page 5 - Electrical Specifications
Contents v July 2005 SLES140 Section Page 2.11.59 Analog Output Control 1 Register 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.11.60 Chip ID MSB Register 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 6 - Example Register Settings
Contents vi July 2005 SLES140 Section Page 3.3 Electrical Characteristics 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 DC Electrical Characteristics 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 7 - List of Illustrations; Figure
List of Illustrations vii July 2005 SLES140 List of Illustrations Figure Title Page 1−1 Functional Block Diagram 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−2 Terminal Assignments Diagram 5 . . . . . . . . . . . . . . ...
Page 8 - List of Tables; Table
List of Tables viii July 2005 SLES140 List of Tables Table Title Page 1−1 Terminal Functions 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−1 Output Format 16 . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 10 - Detailed Functionality
Introduction 2 SLES140A—March 2007 TVP5147M1PFP 1.1 Detailed Functionality • Two 30-MSPS, 10-bit A/D channels with programmable gain control • Supports NTSC (J, M, 4.43), PAL (B, D, G, H, I, M, N, Nc, 60) and SECAM (B, D, G, K, K1, L) CVBS, andS-video • Supports analog component YPbPr video format w...
Page 11 - Related Products; 0-Bit Digital VIdeo Decoder With Macrovision; Ordering Information
Introduction 3 SLES140A—March 2007 TVP5147M1PFP • VBI data processor − Teletext (NABTS, WST) − CC and extended data service (EDS) − Wide screen signaling (WSS) − Copy generation management system (CGMS) − Video program system (VPS/PDC) − Vertical interval time code (VITC) − Gemstar 1 × /2 × mode −...
Page 12 - Functional Block Diagram; Figure 1−1. Functional Block Diagram
Introduction 4 SLES140A—March 2007 TVP5147M1PFP 1.5 Functional Block Diagram Composite and S-Video Processor Y/C Separation 5-line Adaptive Comb Luma Processing Chroma Processing M U X CVBS/Y C/CbCr C Y Output Formatter Y[9:0] VBI Data Processor Copy Protection Detector C[9:0] Host Interface Timing ...
Page 13 - Terminal Assignments; Figure 1−2. Terminal Assignments Diagram
Introduction 5 SLES140A—March 2007 TVP5147M1PFP 1.6 Terminal Assignments 22 23 C_6/GPIOC_7/GPIOC_8/GPIOC_9/GPIODGNDDVDDY_0Y_1Y_2Y_3Y_4IOGNDIOVDDY_5Y_6Y_7Y_8Y_9DGNDDVDD 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VI_1_B VI_1_C CH1_...
Page 14 - Terminal Functions; Table 1−1. Terminal Functions
Introduction 6 SLES140A—March 2007 TVP5147M1PFP 1.7 Terminal Functions Table 1−1. Terminal Functions TERMINAL I/O DESCRIPTION NAME NUMBER I/O DESCRIPTION Analog Video VI_1_AVI_1_BVI_1_CVI_2_AVI_2_B 80 1278 I/O IIII VI_1_A: Analog video input for CVBS/Pb/C or analog video output (see Section 2.11.59)...
Page 17 - Functional Description; Analog Processing and A/D Converters; Figure 2−1. Analog Processors and A/D Converters; C interface. The 10 analog video inputs can be used for different
Functional Description 9 SLES140A—March 2007 TVP5147M1PFP 2 Functional Description 2.1 Analog Processing and A/D Converters Figure 2−1 shows a functional diagram of the analog processors and A/D converters, which provide the analoginterface to all video inputs. It accepts up to 10 inputs and perform...
Page 19 - Digital Video Processing; Figure 2−2. Digital Video Processing Block Diagram; Decimation Filter; the pixel rate. The decimation filter is a half-band filter.
Functional Description 11 SLES140A—March 2007 TVP5147M1PFP 2.2 Digital Video Processing Figure 2−2 is a block diagram of the TVP5147M1 digital video decoder processing. This block receivesdigitized video signals from the ADCs and performs composite processing for CVBS and S-video inputs andYCbCr sig...
Page 20 - Figure 2−3. Composite and S-Video Processing Block Diagram; Color Low-Pass Filter
Functional Description 12 SLES140A—March 2007 TVP5147M1PFP Line Delay – Peaking NTSC/PAL Remodulation NTSC/PAL Demodulation Notch Filter Color LPF ↓ 2 5-Line Adaptive Comb Filter Notch Filter Notch Filter Notch Filter Contrast Brightness Saturation Adjust Cr Y Cb Y Burst Accumulator (U) U SECAM Colo...
Page 22 - Figure 2−8. Luminance Edge-Enhancer Peaking Block Diagram; Color transient improvement
Functional Description 14 SLES140A—March 2007 TVP5147M1PFP 2.2.3 Luminance Processing The digitized composite video signal passes through either a luminance comb filter or a chroma trap filter,either of which removes chrominance information from the composite signal to generate a luminance signal.Th...
Page 23 - Clock Circuits; where C; Figure 2−10. Reference Clock Configurations; is the frequency of the subcarrier PLL, F; is the 23-bit PLL frequency control word, and F; is; Figure 2−11. RTC Timing; Output Formatter
Functional Description 15 SLES140A—March 2007 TVP5147M1PFP 2.3 Clock Circuits An internal line-locked PLL generates the system and pixel clocks. A 14.318-MHz clock is required to drivethe PLL. This can be input to the TVP5147M1 decoder at the 1.8-V level on terminal 74 (XTAL1), or a crystalof 14.318...
Page 24 - Table 2−1. Output Format; VS, HS, and VBLK are independently software programmable to a 1
Functional Description 16 SLES140A—March 2007 TVP5147M1PFP Table 2−1. Output Format TERMINAL NAME TERMINAL NUMBER 10-Bit 4:2:2 YCbCr 20-Bit 4:2:2 YCbCr Y_9 43 Cb9, Y9, Cr9 Y9 Y_8 44 Cb8, Y8, Cr8 Y8 Y_7 45 Cb7, Y7, Cr7 Y7 Y_6 46 Cb6, Y6, Cr6 Y6 Y_5 47 Cb5, Y5, Cr5 Y5 Y_4 50 Cb4, Y4, Cr4 Y4 Y_3 51 Cb3...
Page 25 - Figure 2−12. Vertical Synchronization Signals for 525-Line System
Functional Description 17 SLES140A—March 2007 TVP5147M1PFP First Field Video 525 VS VBLK FID 1 2 3 4 5 6 7 8 9 10 20 21 525-Line HS VS Start VS Stop CS VBLK Start VBLK Stop Second Field Video 262 VS VBLK FID 263 264 265 266 267 268 269 270 271 272 273 283 284 HS VS Start VS Stop CS VBLK Start VBLK S...
Page 26 - Figure 2−13. Vertical Synchronization Signals for 625-Line System
Functional Description 18 SLES140A—March 2007 TVP5147M1PFP First Field Video VS VBLK FID 625-Line HS VS Start VS Stop CS VBLK Start VBLK Stop Second Field Video 310 VS VBLK FID 311 312 313 314 315 316 317 318 319 320 336 337 HS VS Start VS Stop CS VBLK Start VBLK Stop 622 623 624 625 1 2 3 4 5 6 7 2...
Page 29 - Figure 2−16. VSYNC Position With Respect to HSYNC; The P bits are protection bits:; Table 2−3. EAV and SAV Sequence; C Host Interface; Communication with the TVP5147M1 decoder is via an I
Functional Description 21 SLES140A—March 2007 TVP5147M1PFP NTSC 601 64 PAL 601 10-Bit (PCLK = 2 × Pixel Clock) 64 Mode B/2 First Field B/2 858 864 H/2 32 20-Bit (PCLK = 1 × Pixel Clock) 32 B/2 429 432 H/2 HS VS Second Field HS VS B/2 H/2 + B/2 H/2 + B/2 Figure 2−16. VSYNC Position With Respect to HS...
Page 30 - C Host Interface Terminal Description; C Bus Address Selection; C Address Selection; C Operation
Functional Description 22 SLES140A—March 2007 TVP5147M1PFP Table 2−4. I 2 C Host Interface Terminal Description SIGNAL TYPE DESCRIPTION I2CA I Slave address selection SCL I Input clock line SDA I/O Input/output data line 2.6.1 Reset and I 2 C Bus Address Selection The TVP5147M1 decoder can respond t...
Page 31 - Figure 2−17. VBUS Access
Functional Description 23 SLES140A—March 2007 TVP5147M1PFP Single Byte B8 S ACK E8 ACK VA0 ACK VA1 ACK VA2 ACK P VBUS Write B8 S ACK E0 ACK Send Data ACK P Multiple Bytes B8 S ACK E8 ACK VA0 ACK VA1 ACK VA2 ACK P B8 S ACK E1 ACK Send Data ACK ACK P Send Data • • • Single Byte B8 S ACK E8 ACK VA0 ACK...
Page 32 - VBI Data Processor; Table 2−6. Supported VBI System
Functional Description 24 SLES140A—March 2007 TVP5147M1PFP 2.7 VBI Data Processor The TVP5147M1 VBI data processor (VDP) slices various data services like teletext (WST, NABTS), closedcaption (CC), wide screen signaling (WSS), program delivery control (PDC), vertical interval time code (VITC),video ...
Page 33 - VBI FIFO and Ancillary Data in Video Stream; Table 2−7. Ancillary Data Format and Sequence; Even parity for D0−D5, NEP: Negated even parity
Functional Description 25 SLES140A—March 2007 TVP5147M1PFP 2.7.1 VBI FIFO and Ancillary Data in Video Stream Sliced VBI data can be output as ancillary data in the video stream in ITU-R BT.656 mode. VBI data is outputon the Y[9:2] terminals during the horizontal blanking period. Table 2−7 shows the ...
Page 34 - Table 2−8. VBI Raw Data Output Format; Reset and Initialization; Table 2−9. Reset Sequence
Functional Description 26 SLES140A—March 2007 TVP5147M1PFP 2.7.2 VBI Raw Data Output The TVP5147M1 decoder can output raw A/D video data at twice the sampling rate for external VBI slicing.This is transmitted as an ancillary data block, although somewhat differently from the way the sliced VBI datai...
Page 35 - Adjusting External Syncs; The proper sequence to program the following external syncs is:; Internal Control Registers; C Register Summary
Functional Description 27 SLES140A—March 2007 TVP5147M1PFP 2.9 Adjusting External Syncs The proper sequence to program the following external syncs is: • To set NTSC, PAL-M, NTSC 443, PAL60 (525-line modes): − Set the video standard to NTSC (register 02h) − Set HSYNC, VSYNC, VBLK, and AVID external ...
Page 38 - Table 2−11. VBUS Register Summary
Functional Description 30 SLES140A—March 2007 TVP5147M1PFP Table 2−10. I 2 C Register Summary (Continued) REGISTER NAME I2C SUBADDRESS DEFAULT R/W VBUS data access with no VBUS address increment E0h 00h R/W VBUS data access with VBUS address increment E1h 00h R/W FIFO read data E2h R Reserved E3h−E7...
Page 39 - Register Definitions; Input Select Register; Table 2−12. Analog Channel and Video Mode Selection
Functional Description 31 SLES140A—March 2007 TVP5147M1PFP 2.11 Register Definitions 2.11.1 Input Select Register Subaddress 00h Default 00h 7 6 5 4 3 2 1 0 Input select [7:0] Table 2−12. Analog Channel and Video Mode Selection MODE INPUT(S) SELECTED INPUT SELECT [7:0] OUTPUT MODE INPUT(S) SELECTED ...
Page 40 - AFE Gain Control Register; Component Video; Reserved
Functional Description 32 SLES140A—March 2007 TVP5147M1PFP 2.11.2 AFE Gain Control Register Subaddress 01h Default 0Fh 7 6 5 4 3 2 1 0 Reserved 1 1 AGC chroma AGC luma Bit 3: 1 must be written to this bit. Bit 2: 1 must be written to this bit. AGC chroma enable: Controls automatic gain in the chroma...
Page 41 - Operation Mode Register
Functional Description 33 SLES140A—March 2007 TVP5147M1PFP 2.11.4 Operation Mode Register Subaddress 03h Default 00h 7 6 5 4 3 2 1 0 Reserved Power save Power save: 0 = Normal operation (default)1 = Power-save mode. Reduces the clock speed of the internal processor and switches off the ADCs. I 2 C i...
Page 42 - Color Killer Register; Automatic color killer:; Luminance Processing Control 1 Register; Pedestal not present:
Functional Description 34 SLES140A—March 2007 TVP5147M1PFP 2.11.6 Color Killer Register Subaddress 05h Default 10h 7 6 5 4 3 2 1 0 Reserved Automatic color killer Color killer threshold [4:0] Automatic color killer: 00 = Automatic mode (default)01 = Reserved10 = Color killer enabled, the UV terminal...
Page 43 - Luminance Processing Control 2 Register
Functional Description 35 SLES140A—March 2007 TVP5147M1PFP 2.11.8 Luminance Processing Control 2 Register Subaddress 07h Default 00h 7 6 5 4 3 2 1 0 Luma filter select [1:0] Reserved Peaking gain [1:0] Reserved Luma filter selected [1:0]: 00 = Luminance adaptive comb enabled (default on CVBS)01 = Lu...
Page 44 - Luminance Contrast Register
Functional Description 36 SLES140A—March 2007 TVP5147M1PFP 2.11.11 Luminance Contrast Register Subaddress 0Ah Default 80h 7 6 5 4 3 2 1 0 Contrast [7:0] Contrast [7:0]: This register works for CVBS, S-video, and component video luminance. 1111 1111 = 255 (maximum contrast)1000 0000 = 128 (default)00...
Page 45 - 5 Chrominance Processing Control 2 Register; See Figure 2−6 and Figure 2−7 for characteristics.; NTSC Sqp
Functional Description 37 SLES140A—March 2007 TVP5147M1PFP 2.11.15 Chrominance Processing Control 2 Register Subaddress 0Eh Default 0Eh 7 6 5 4 3 2 1 0 Reserved PAL compensation WCF Chrominance filter select [1:0] PAL compensation: 0 = Disabled1 = Enabled (default) Wideband chroma LPF filter (WCF): ...
Page 48 - Polarity FID: determines polarity of FID terminal
Functional Description 40 SLES140A—March 2007 TVP5147M1PFP 2.11.25 CTI Control Register Subaddress 2Eh Default 00h 7 6 5 4 3 2 1 0 CTI coring [3:0] CTI gain [3:0] CTI coring [3:0]: 4-bit CTI coring limit control value, unsigned linear control range from 0 to ± 60, step size = 4 1111 = ± 60 0001 = ± ...
Page 49 - YCbCr output code range:
Functional Description 41 SLES140A—March 2007 TVP5147M1PFP 2.11.27 Output Formatter 1 Register Subaddress 33h Default 40h 7 6 5 4 3 2 1 0 Reserved YCbCr code range CbCr code Reserved Output format [2:0] YCbCr output code range: 0 = ITU-R BT.601 coding range (Y ranges from 64 to 940. Cb and Cr range ...
Page 54 - Read only
Functional Description 46 SLES140A—March 2007 TVP5147M1PFP 2.11.34 Status 1 Register Subaddress 3Ah Read only 7 6 5 4 3 2 1 0 Peak white detect status Line-alternating status Field rate status Lost lock detect Color subcarrier lock status Vertical sync lock status Horizontal sync lock status TV/VCR ...
Page 58 - 0 AFE Coarse Gain for CH 1 Register; CGAIN 1; 1 AFE Coarse Gain for CH 2 Register; CGAIN 2
Functional Description 50 SLES140A—March 2007 TVP5147M1PFP 2.11.40 AFE Coarse Gain for CH 1 Register Subaddress 46h Default 20h 7 6 5 4 3 2 1 0 CGAIN 1 [3:0] Reserved CGAIN 1 [3:0]: Coarse_Gain = 0.5 + (CGAIN 1)/10, where 0 ≤ CGAIN 1 ≤ 15 This register works only in manual gain control mode. When AG...
Page 59 - 2 AFE Coarse Gain for CH 3 Register; CGAIN 3; 3 AFE Coarse Gain for CH 4 Register; CGAIN 4
Functional Description 51 SLES140A—March 2007 TVP5147M1PFP 2.11.42 AFE Coarse Gain for CH 3 Register Subaddress 48h Default 20h 7 6 5 4 3 2 1 0 CGAIN 3 [3:0] Reserved CGAIN 3 [3:0]: Coarse_Gain = 0.5 + (CGAIN 3)/10, where 0 ≤ CGAIN 3 ≤ 15 This register works only in the manual gain control mode. Whe...
Page 60 - FGAIN 1
Functional Description 52 SLES140A—March 2007 TVP5147M1PFP 2.11.44 AFE Fine Gain for Pb Register Subaddress 4Ah−4Bh Default 900h Subaddress 7 6 5 4 3 2 1 0 4Ah FGAIN 1 [7:0] 4Bh Reserved FGAIN 1 [11:8] FGAIN 1 [11:0]: This fine gain applies to component Pb. Fine_Gain = (1/2048) * FGAIN 1, where 0 ≤ ...
Page 61 - FID control
Functional Description 53 SLES140A—March 2007 TVP5147M1PFP 2.11.47 AFE Fine Gain for CVBS_Luma Register Subaddress 50h−51h Default 900h Subaddress 7 6 5 4 3 2 1 0 50h FGAIN 4 [7:0] 51h Reserved FGAIN 4 [11:8] FGAIN 4 [11:0]: This fine gain applies to CVBS or S-video luma (see AFE fine gain for Pb re...
Page 62 - VPLL: VPLL time constant control
Functional Description 54 SLES140A—March 2007 TVP5147M1PFP 2.11.49 F-bit and V-bit Control 1 Register Subaddress 69h Default 00h 7 6 5 4 3 2 1 0 Reserved VPLL Adaptive Reserved F-bit mode [1:0] VPLL: VPLL time constant control 0 = VPLL adapts the time constant to the input signal (default)1 = VPLL t...
Page 63 - 1 AGC Decrement Speed Control Register
Functional Description 55 SLES140A—March 2007 TVP5147M1PFP 2.11.50 Back-End AGC Control Register Subaddress 6Ch Default 08h 7 6 5 4 3 2 1 0 Reserved 1 Peak Color Sync This register disables the back-end AGC when the front-end AGC uses specific amplitude references(sync-height, color burst, or compos...
Page 64 - 3 AGC White Peak Processing Register
Functional Description 56 SLES140A—March 2007 TVP5147M1PFP 2.11.53 AGC White Peak Processing Register Subaddress 74h Default 00h 7 6 5 4 3 2 1 0 Luma peak A Reserved Color burst A Sync height A Luma peak B Composite peak Color burst B Sync height B Luma peak A: Use of the luma peak as a video amplit...
Page 65 - Rabbit: Enable rabbit ear; Phase detector: Enable integral window phase detector
Functional Description 57 SLES140A—March 2007 TVP5147M1PFP 2.11.54 F and V Bit Control Register Subaddress 75h Default 12h 7 6 5 4 3 2 1 0 Rabbit Reserved Fast lock F and V [1:0] Phase Det. HPLL Rabbit: Enable rabbit ear 0 = Disabled (default)1 = Enabled Fast lock: Enable fast lock where vertical PL...
Page 66 - 6 Horizontal Shake Increment Register; AGC increment speed: Adjusts gain increment speed.
Functional Description 58 SLES140A—March 2007 TVP5147M1PFP 2.11.55 VCR Trick Mode Control Register Subaddress 76h Default 8Ah 7 6 5 4 3 2 1 0 Switch header Horizontal shake threshold [6:0] Switch header: When in VCR trick mode, the header noisy area around the head switch is skipped. 0 = Disabled1 =...
Page 67 - Analog output enable:
Functional Description 59 SLES140A—March 2007 TVP5147M1PFP 2.11.59 Analog Output Control 1 Register Subaddress 7Fh Default 00h 7 6 5 4 3 2 1 0 Reserved AGC enable Input select Analog Output enable AGC enable: 0 = Enabled (default)1 = Disabled, manual gain mode (see Section 2.12.10) Input select: 00 ...
Page 69 - 6 VDP TTX Filter And Mask Registers
Functional Description 61 SLES140A—March 2007 TVP5147M1PFP 2.11.66 VDP TTX Filter And Mask Registers Subaddress B1h B2h B3h B4h B5h B6h B7h B8h B9h BAh Default 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h Subaddress 7 6 5 4 3 2 1 0 B1h Filter 1 mask 1 Filter 1 pattern 1 B2h Filter 1 mask 2 Filter 1 patte...
Page 70 - Mode: indicates which teletext mode is in use.
Functional Description 62 SLES140A—March 2007 TVP5147M1PFP 2.11.67 VDP TTX Filter Control Register Subaddress BBh Default 00h 7 6 5 4 3 2 1 0 Reserved Filter logic [1:0] Mode TTX filter 2 enable TTX filter 1 enable Filter logic [1:0]: Allow different logic to be applied when combining the decision o...
Page 71 - Figure 2−19. Teletext Filter Function
Functional Description 63 SLES140A—March 2007 TVP5147M1PFP 1P1[3] 1M1[0] 1M1[1] 1M1[2] 1M1[3] NIBBLE 1 FILTER 2 FILTER 1 00 01 10 11 PASS 1 Filter 1Enable 2 Filter Logic PASS 1P1[2] 1P1[1] 1P1[0] D1[3] D1[2] D1[1] D1[0] NIBBLE 2 D2[3:0] 1P2[3:0] 1M2[3:0] NIBBLE 3 NIBBLE 4 NIBBLE 5 D3[3:0] 1P3[3:0] 1...
Page 72 - 9 VDP FIFO Interrupt Threshold Register; Field 1 interrupt enable:
Functional Description 64 SLES140A—March 2007 TVP5147M1PFP 2.11.69 VDP FIFO Interrupt Threshold Register Subaddress BDh Default 80h 7 6 5 4 3 2 1 0 Threshold [7:0] Threshold [7:0]: This register is programmed to trigger an interrupt when the number of words in the FIFOexceeds this value. NOTE: 1 wor...
Page 74 - 9 VBUS Data Access With No VBUS Address Increment Register
Functional Description 66 SLES140A—March 2007 TVP5147M1PFP 2.11.77 VDP Full Field Enable Register Subaddress D9h Default 00h 7 6 5 4 3 2 1 0 Reserved Full field enable Full field enable: 0 = Disabled full field mode (default)1 = Enabled full field mode This register enables the full field mode. In t...
Page 80 - Line: Line number interrupt clear
Functional Description 72 SLES140A—March 2007 TVP5147M1PFP Line: Line number interrupt clear 0 = Disabled (default)1 = Clear bit 0 (line interrupt available) in the interrupt status 0 register at subaddress F2h The host interrupt clear 0 and 1 registers are used by the external processor to clear th...
Page 81 - VBUS Register Definitions; VDP Closed Caption Data Register; VDP WSS Data Register; These registers contain the wide screen signaling data for NTSC.
Functional Description 73 SLES140A—March 2007 TVP5147M1PFP 2.12 VBUS Register Definitions 2.12.1 VDP Closed Caption Data Register Subaddress 80 051Ch−80 051Fh Read only Subaddress 7 6 5 4 3 2 1 0 80 051Ch Closed caption field 1 byte 1 80 051Dh Closed caption field 1 byte 2 80 051Eh Closed caption fi...
Page 82 - VDP VITC Data Register; VDP V-Chip TV Rating Block 1 Register
Functional Description 74 SLES140A—March 2007 TVP5147M1PFP 2.12.3 VDP VITC Data Register Subaddress 80 052Ch−80 0534h Read only Subaddress 7 6 5 4 3 2 1 0 80 052Ch VITC frame byte 1 80 052Dh VITC frame byte 2 80 052Eh VITC seconds byte 1 80 052Fh VITC seconds byte 2 80 0530h VITC minutes byte 1 80 0...
Page 83 - VDP V-Chip TV Rating Block 3 Register; VDP V-CHIP MPAA Rating Data Register
Functional Description 75 SLES140A—March 2007 TVP5147M1PFP 2.12.6 VDP V-Chip TV Rating Block 3 Register Subaddress 80 0542h Read only 7 6 5 4 3 2 1 0 None TV-MA TV-14 TV-PG TV-G TV-Y7 TV-Y None TV parental guidelines rating block 3: None: no block intended TV-MA: When incoming video program is TV-MA...
Page 84 - VDP General Line Mode and Line Address Register
Functional Description 76 SLES140A—March 2007 TVP5147M1PFP 2.12.8 VDP General Line Mode and Line Address Register Subaddress 80 0600h−80 0611h (default line mode = FFh, address = 00h) Subaddress 7 6 5 4 3 2 1 0 80 0600h Line address 1 80 0601h Line mode 1 80 0602h Line address 2 80 0603h Line mode 2...
Page 85 - VDP VPS/Gemstar Data Register
Functional Description 77 SLES140A—March 2007 TVP5147M1PFP 2.12.9 VDP VPS/Gemstar Data Register Subaddress 80 0700h−80 070Ch VPS: Read only Subaddress 7 6 5 4 3 2 1 0 80 0700h VPS byte 1 80 0701h VPS byte 2 80 0702h VPS byte 3 80 0703h VPS byte 4 80 0704h VPS byte 5 80 0705h VPS byte 6 80 0706h VPS ...
Page 86 - CH1 selected
Functional Description 78 SLES140A—March 2007 TVP5147M1PFP 2.12.10 Analog Output Control 2 Register Subaddress A0 005Eh Default B2h 7 6 5 4 3 2 1 0 Reserved Reserved Input Select [1:0] Gain [3:0] Analog input select [1:0]: These bits are effective when manual input select bit is set to 1 at subaddre...
Page 87 - Absolute Maximum Ratings; Recommended Operating Conditions
Electrical Specifications 79 SLES140A—March 2007 TVP5147M1PFP 3 Electrical Specifications 3.1 Absolute Maximum Ratings † Supply voltage range: IOV DD to I/O GND 0.5 V to 4 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DV DD to DGND −0.2 V to 2 V . . . . ...
Page 88 - Electrical Characteristics; AV
Electrical Specifications 80 SLES140A—March 2007 TVP5147M1PFP 3.3 Electrical Characteristics For minimum/maximum values: IOV DD = 3 V to 3.6 V, DV DD = 1.65 V to 1.95 V, AV DD33 = 3 V to 3.6 V, AV DD18 = 1.65 V to 1.95 V, T A = 0 ° C to 70 ° C For typical values: IOV DD = 3.3 V, DV DD = 1.8 V, AV DD...
Page 89 - C Host Port Timing
Electrical Specifications 81 SLES140A—March 2007 TVP5147M1PFP 3.3.3 Timing 3.3.3.1 Clocks, Video Data, Sync Timing PARAMETER TEST CONDITIONS (see NOTE 1) MIN TYP MAX UNIT Duty cycle DATACLK 45% 50% 55% t1 High time, DATACLK 18.5 ns t2 Low time, DATACLK 18.5 ns t3 Fall time, DATACLK 90% to 10% 4 ns t...
Page 91 - Example 1
Example Register Settings 83 SLES140A—March 2007 TVP5147M1PFP 4 Example Register Settings The following example register settings are provided only as a reference. These settings, given the assumedinput connector, video format, and output format, set up the TVP5147M1 decoder and provide video output...
Page 92 - Example 3
Example Register Settings 84 SLES140A—March 2007 TVP5147M1PFP I 2 C register address 00h = Input select register I 2 C data 46h = Sets luma to VI_2_C and chroma to VI_1_C I 2 C register address 04h = Autoswitch mask register I 2 C data 3Fh = Includes NTSC 443 and PAL (M, Nc, 60) in the autoswitch I ...
Page 95 - Application Information; Application Example; Figure 5−1. Example Application Circuit
Application Information 87 SLES140A—March 2007 TVP5147M1PFP 5 Application Information 5.1 Application Example 75 Ω (3) 0.1 µ F (3) 75 Ω (3) 2.2 k Ω NOTE: If XTAL1 is connected to clock source, input voltage high must be 1.8 V. TVP5147 can be a drop-in replacement for TVP5146.Terminals 69 and 71 must...
Page 96 - Designing With PowerPAD; PCB features, the use of solder
Application Information 88 SLES140A—March 2007 TVP5147M1PFP 5.2 Designing With PowerPAD t Devices The TVP5147 device is housed in a high-performance, thermally enhanced, 80-terminal PowerPAD package(TI package designator: 80PFP). Use of the PowerPAD package does not require any special consideration...
Page 97 - PACKAGING INFORMATION; PACKAGE OPTION ADDENDUM
PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) TVP5147M1PFP ACTIVE HTQFP PFP 80 96 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TVP5147M1PFPG4 ACTIVE HTQFP PFP 80 96 Green (RoHS & no Sb/...
