Page 2 - Edition; Page
Edition (04/2007) Disclaimer of Liability We have checked the contents of this manual for agreement with the hardware and software described. Since deviations cannot be precluded entirely, we cannot guarantee full agreement. However, the data in this manual are reviewed regularly. Necessary correcti...
Page 3 - Products; Low Voltage
Turfschipper 41 2292 JC Wateringen The Netherlands tel. +31 (0)174 671 800 fax. +31 (0)174 671 801 e-mail [email protected] Page 1 / 2 ING bank Rijswijk (ZH) 67.87.34.909 – Chamber of commerce The Hague nr. 27165526 – BTW/VAT NL816153073.B01 Conditions are applied on all offers and orders, which are...
Page 5 - Preface; Target Audience of this Manual
Preface Target Audience of this Manual This manual is intended for hardware developers who want to use the ERTEC 200 for new products. Experience working with processors and designing embedded systems and knowledge of Ethernet are required for this. It described all ERTEC function groups in details ...
Page 6 - Technical Contacts for Germany / Worldwide; Siemens AG; ComDeC
This manual will be updated as required. You can find the current version of the manual on the Internet at http://www.siemens.com/comdec . Guide To help you quickly find the information you need, this manual contains the following aids: o A complete table of contents as well as a list of all figures...
Page 7 - Contents
Contents 1 Introduction ............................................................................................................................ 9 1.1 Applications of the ERTEC 200 .............................................................................................................. 9 1....
Page 10 - Table 13: Baud Rates for UART at F
List of Figures Figure 1: ERTEC 200 Block Diagram .................................................................................................................... 10 Figure 2: ERTEC 200 Package Description .............................................................................................
Page 11 - Introduction; Applications of the ERTEC 200
1 Introduction The ERTEC 200 is intended for the implementation of PROFINET devices with RT and IRT functionality. With its integrated ARM946 processor and 2-port Ethernet switch with integrated PHYs and the option to connect an external host processor system to a local bus interface, it meets all t...
Page 12 - Controller; with
1.3 Structure of the ERTEC 200 The figure below shows the function groups with the common communication paths. DMA- Controller AHB/APB Bridge GPIO Ma s te r Master P P o r t s 7 APB 50MHz / 32 Bit 74 LBU / MII + SMI / ETM / GPIO 1 x UART SPI1 Interface 3 x Timer, Watchdog, F-Timer AR M 9 cl o c k 50...
Page 13 - Soldering instructions for lead-based block.; When working with modules,; always take precautionary measures; against electrostatic charge; ESD; lectrostatic
1.4 ERTEC 200 Package The ERTEC 200 is supplied in an FBGA package with 304 pins. The distance between the pins is 0.8 mm. The package dimensions are 19 mm x 19 mm. Figure 2: ERTEC 200 Package Description Soldering instructions for the ERTEC 200 can be found in the following documents: /10/ Solderin...
Page 14 - Signal Function Description; ERTEC 200 Pin Description; and; PIN
1.5 Signal Function Description ERTEC 200 Pin Description The ERTEC 200 Ethernet communication block is available in a 304-pin FBGA package. The signal names of the ERTEC 200 are described in this section. 1.5.1 GPIO 0 to 31 and Alternative Functions Various signals are multiplexed on the same pin. ...
Page 25 - CP15 control register
2.6 Memory Protection Unit (MPU) The memory protection unit enables the user to partition specific memory areas (I-cache, D-cache, or DTCM) into various regions and to assign different attributes to them. A maximum of 8 regions of variable size can be set. If regions overlap, the attributes of the h...
Page 33 - Register
2.10 ARM946E-S Register The ARM946E-S uses CP15 registers for system control. Consequently, the following settings are possible: • Configure cache type and cache memory area • Configure tightly coupled memory area • Configure memory protection unit for various regions and memory types • Assign syste...
Page 34 - X X
3 Bus System of the ERTEC 200 Internally, the ERTEC 200 has two buses. High-performance communication bus (multilayer AHB bus) I/O bus (APB bus) The following function blocks are connected directly to the multilayer AHB bus: ARM946E-S (Master) IRT switch (Master/Slave) LBU (Master) Inter...
Page 35 - ROM
4 I/O on APB bus The ERTEC 200 block has multiple I/O function blocks. They are connected to the 32-bit APB I/O bus. The ARM946E-S, DMA controller and LBU interface can access the I/O. The following I/O are available. 8 Kbyte Boot ROM 32-bit GPIO (*) UART SPI interface Timer 0 - 2 F-time...
Page 37 - P in of
4.2 General Purpose I/O (GPIO) Up to 45 General Purpose Inputs/Outputs are available in the ERTEC 200. These are divided into two groups: • GPIO[31:0] 32 bits on the APB I/O bus • GPIO[44:32] 13 bits as an alternative function on the LBU interface The GPIOs [31 : 0] can be used as follows • Inputs •...
Page 40 - Reserved; Timer 0 and Timer 1
GPIO2_ IN R Addr.: 0x4000_2528 Default: Port assignment Description Input register for General Purpose IO [44:32] Bit No. Name Description 31..13 Reserved Reserved 12..0 GPIO2_IN[44:32] 0: GPIO inputx = 0, 1: GPIO inputx = 1 4.3 Timer 0/1/2 Three independent timers are integrated in the ERTEC 200. T...
Page 41 - Cascading of Timers 0/1
4.3.1.1 Timer 0/1 Interrupts The timer 0/1 interrupt is active (High) starting from the point at which the timer value is counted down to 0. The timer interrupt is deactivated (Low) when the reload value is automatically reloaded or the "LOAD“ bit is set by the user. The interrupt is not reset w...
Page 45 - External counter cable
4.4 F-Timer Function An F-timer is integrated in the ERTEC 200 in addition to the system timers. This timer works independently of the system clock and can be used for fail-safe applications, for example. The F-timer is triggered via the alternative “F_CLK” function at the external “BYP_CLK” input. ...
Page 46 - The F-timer registers are; 2 bits in width; . The registers can be written to in 32-bit width; only
4.4.1 Address Assignment of F-Timer Registers The F-timer registers are 32 bits in width . The registers can be written to in 32-bit width only . F-Counter (Base Address 0x4000_2700) Register Name Offset Address Address Area Access Default Description F-COUNTER-VAL 0x0000 4 bytes R 0x00000000 F-coun...
Page 47 - Timers; Watchdog Timer 0
4.5 Watchdog Timers Two watchdog timers are integrated in the ERTEC 200. The watchdog timers are intended for stand-alone monitoring of processes. The working clock of 50 MHz is derived from the PLL the same as the processor clock. 4.5.1 Watchdog Timer 0 Watchdog timer 0 is a 32-bit down-counter to ...
Page 48 - Register Name
4.5.6 Watchdog Registers The watchdog registers are 32 bits in width. For read/write access of the watchdog registers to be meaningful, a 32-bit access is required. However, a byte-by-byte write operation is not intercepted by the hardware. To prevent the watchdog registers from being written to ina...
Page 50 - Interface; TXD
4.6 UART Interface A UART interface is implemented in the ERTEC 200. The inputs and outputs of the UART interface are available as an alternative function at GPIO port [12:8]. For this purpose, the I/O must be assigned to the relevant inputs and outputs and the alternative function must be assigned ...
Page 51 - Address Assignment of UART Registers
The baud rate generation is derived from the internal 50 MHz APB clock. The resulting deviations from the standard baud rates used are so small that a secure data transmission is achieved. The baud rate is calculated according to the following formula: F UARTCLK F UARTCLK BR = ----------------------...
Page 52 - UART Register Description; UARTDR; Name; Name
4.6.2 UART Register Description UARTDR R/W Addr.: 0x4000_2300 Default: 0x-- Description UART data registers Bit No. Name Description 7 – 0 ------- WRITE: - If FIFO is enabled, the written data are entered in the FIFO. - If FIFO is disabled, the written data are entered in the Transmit holding regist...
Page 55 - UARTILPR
UARTIIR/UARTICR R/W Addr.: 0x4000_231C Default: 0x00 Description UART interrupt identification register (read) UART interrupt clear register (write) Bit No. Name Description 0 MIS (Read) Modem Interrupt Status This bit is set if UARTMSINTR is active. 1 RIS (Read) Receive Interrupt Status This bit is...
Page 56 - Synchronous Interface SPI; SSPTXD
4.7 Synchronous Interface SPI An SPI interface is implemented in the ERTEC 200. The inputs and outputs of the SPI interface are available as an alternative function at GPIO port [23:16]. For this purpose, the I/O must be assigned to the relevant inputs and outputs and the alternative function must b...
Page 57 - 6 bits in width; . Reading or writing the SPI register is useful only in 16-bit access
For the synchronous clock output of the SPI interface, the following frequencies are calculated according to the assigned SPI registers: 50 MHz SCLKOUT = ----------------------------- CPSDRV * (1+SCR) The SPI parameters can assume the following values: CPSDRV From 2 to 254 SCR From 0 to 255 This yie...
Page 58 - SPI Register Description
4.7.2 SPI Register Description SSPCR0 R/W Addr.: 0x4000_2200 Default: 0x0000 Description Control register 0. Configuration frame format and baud rate for SPI. Bit No. Name Description 3 - 0 DSS Data Size Select 0000 Reserved (undefined) 1000 9-Bit Data 0001 Reserved (undefined) 1001 10-Bit Data 0010...
Page 60 - Read: Reserved Value is undefined; System control register; Address Assignment of System Control Registers; The system control registers are
SSPIIR/SSPICR R/W Addr.: 0x4000_2214 Default: 0x0000 Description SPI interrupt identification register (read) SPI interrupt clear register (write) Bit No. Name Description 0 RIS (Read) SPI Receive FIFO service request interrupt status 0 = SSPRXINTR is not active 1 = SSPRXINTR is active 1 TIS (Read) ...
Page 61 - System Control Register Description
UART_CLK 0x0070 4 bytes R/W 0x00000000 UART clock selection 50MHz/6MHz Table 16: Overview of System Control Registers 4.8.2 System Control Register Description ID_REG R Addr.: 0x4000_2600 Default: 0x4027_0100 Description Identification of ERTEC 200. Bit No. Name Description 31..16 ERTEC200-ID ERTEC ...
Page 65 - UART_CLK
12:10 P2_PHY_MODE 000: 10BASE-T HD, Auto-Neg disabled 001: 10BASE-T FD, Auto-Neg disabled 010: 100BASE-TX/FX HD, Auto-Neg disabled 011: 100BASE-TX/FX FD, Auto-Neg disabled 100: 100BASE-TX HD announced, Auto-Neg enabled 101: 100BASE-TX HD announced, Auto-Neg enabled, Repeater Mode 110: PHY starts in ...
Page 66 - General Hardware Functions; Clock Generation and Clock Supply; Clock Supply in ERTEC 200; Table 17: Overview of ERTEC 200 Clocks
5 General Hardware Functions 5.1 Clock Generation and Clock Supply The clock system of the ERTEC 200 basically consists of four clock systems that are decoupled through asynchronous transfers. This includes the following clock systems: • ARM946E-S together with AHB bus, APB bus, and IRT • LBU • JTAG...
Page 67 - CONFIG1; MII Mode; at least 35 μs; reset
5.1.2 JTAG Clock Supply The clock supply for the JTAG interface is implemented using the JTAG_CLK pin. The frequency range is between 0 and 10 MHz. The boundary scan and the ICE macro cell of the ARM946E-S are enabled via the JTAG interface. 5.1.3 Clock Supply for PHYs and Ethernet MACs Both Etherne...
Page 68 - active
f/MHz t/µs t LOCK = 645 µs 35 Power-up PLL active Reset 300 Figure 11: Power-Up Phase of the PLL The lock status of the PLL is monitored by the hardware. Loss of the input clock and PLL not locked status is signaled with interrupt FIQ3. The state of the PLL can also be read out in the PII_STAT_REG s...
Page 69 - Configuration Options on the ERTEC 200; nitoring
5.3 Address Sp Monitoring mechan egal accesses, and timeout. The followi • AHB bus • APB bus • EMIF 5.3.1 AHB Bus Mo Separate address space mo DMA, LBU). If an AHB master addresses an un e and an FIQ2 interrupt is triggered at the ARM9 AHB_ADR system control register and the associated access type (...
Page 72 - Address Assignment of EMIF Registers; EMIF Register Description; Revision Code and Status
6.1 Address Assignment of EMIF Registers The EMIF registers are 32 bits in width . These registers can only be written to with double words. EMIF (Base Address 0x7000_0000) Register Name Offset Address Address Area Access Default Description Revision_Code_and _Status 0x0000 4 bytes R 0x00000100 Revi...
Page 75 - Extended Config; Programming specification for EMIR registers:; SDRAM Refresh Control
Extended Config W/R Addr.: 0x7000_0020 Default: 0x0303_0000 Description Setting of additional functionalities Bit No. Name Description 31 Reserved Reserved 30 TEST_1 Test Mode 1 0: 200 µs delay after system reset (SDRAM power-up) 1: Delay after system reset is immediately terminated 29 TEST_2 Test M...
Page 77 - Addressed Segment
The four segments are addressed via the two LBU_SEG[1:0] inputs. LBU_SEG[1 : 0] Addressed Segment 00 LBU_PAGE0 01 LBU_PAGE1 10 LBU_PAGE2 11 LBU_PAGE3 Copyright © Siemens AG 2007. All rights reserved. 75 ERTEC 200 Manual Technical data subject to change Version 1.1.0
Page 78 - Page Range Setting; Size of Page x; Table 20: Setting of Various Page Sizes; address cables; Page Offset Setting; Offset for Page x; Table 21: Setting of Various Offset Areas
7.1 Page Range Setting The page size of each page is set in the PAGEx_RANGE_HIGH and PAGEx_RANGE_LOW range registers (x = 0 to 3). Together, the two page range registers yield a 32-bit address register. The size of the page varies between 256 bytes and 2 MBytes. Therefore, Bits 0 to 7 and Bits 22 to...
Page 79 - LBU Address Mapping; 0 Mirrored; 1 Mirrored; Host
7.3 LBU Address Mapping The following table illustrates an example of the ERTEC 200 Address Mapping from the Perspective of an External Host Processor: Seg(1:0) AD(19:0) SEGMENT Distribution SEGMENT Size Comment 00 0_0000h 1MB 1MB Page SDRAM (1 Mbyte) 00 Range: 0010 0000h 00 F_FFFFh Offset: 2000 000...
Page 80 - Page Control Setting; of the host
7.4 Page Control Setting The user can use the page control register to set the type of access to the relevant page. Certain areas of the ERTEC 200 must be implemented with a 32-bit data access in order to ensure data consistency. For other areas, an 8-bit or 16-bit data access is permitted. The foll...
Page 81 - Table 25: LBU Read access timing with seperate Read/Write line
7.5.1 LBU Read from ERTEC 200 with separate Read/Write line (LBU_RDY_N active low) LBU_CS_R_N/ LBU_CS_M_N LBU_RD_N LBU_A(20:0)A/ LBU_SEG(1:0)/ LBU_BE(1:0)_N LBU_RDY_N LBU_D(15:0) t CSRS t ARS t RRE t RDE t RTD t RDH t RAH t RCSH t RAP t RR Figure 13: LBU-Read-Sequence with separate RD/WR line Parame...
Page 82 - Table 26: LBU Write access timing with seperate Read/Write line
7.5.2 LBU Write to ERTEC 200 with separate Read/Write line (LBU_RDY_N active low) LBU_CS_R_N/ LBU_CD_M_N LBU_WR_N LBU_A(20:0)/ LBU_SEG(1:0) LBU_BE(1:0)_N LBU_RDY_N LBU_D(15:0) t CSWS t AWS t WRE t WDV t WDH t WAH t WCSH t RTW t RAP t WR Figure 14: LBU-Write-Sequence with separate RD/WR line Paramete...
Page 83 - Table 27: LBU Read access timing with common Read/Write line
7.5.3 LBU Read from ERTEC 200 with common Read/Write line (LBU_RDY_N active low) LBU_CS_R_N/ LBU_CS_M_N LBU_WR LBU_A(20:0)/ LBU_SEG(1:0)/ LBU_BE(1:0)_N LBU_RDY LBU_D(15:0) t WCS t ACS t CRE t CDE t RTD t CDH t CAH t CWH t RAP t RR Figure 15: LBU-Read-Sequence with common RD/WR line Parameter Descrip...
Page 84 - Table 28: LBU Write access timing with common Read/Write line; The setup time
7.5.4 LBU Write to ERTEC 200 with common Read/Write line (LBU_RDY_N active low) LBU_CS_R_N/ LBU_CS_M_N LBU_W R_N LBU_A(20:0)/ LBU_SEG(1:0)/ LBU_BE(1:0)_N LBU_RDY LBU_D(15:0) t WCS t ACS t CRE t CDV t CDH t CAH t CWH t RTC t RAP t WR Figure 16: LBU-Write-Sequence with common RD/WR line Parameter Desc...
Page 85 - Address Assignment of LBU Registers; The LBU registers are; LBU; LBU Register Description
7.7 Address Assignment of LBU Registers The LBU registers are 16 bits in width . These registers can only be written to with words. The LBU paging configuration registers are addressed via the "LBU_CS_R_N” input. LBU Register Name Offset Address Address Area Access Default Description LBU_P0_RG_...
Page 88 - DMA Register Address Assignment; Description of DMA Registers
8.1 DMA Register Address Assignment The DMA registers are 32 bits in width . The registers can be written to with 32-bit accesses only. Only the ARM946E-S processor can access the registers. DMA-Register (Start 0x8000_0000) Register Name Offset Address Address Area Access Default Description DMAC0_S...
Page 91 - Bit
• P1/2_PHYADDRESS 4..0 Port1 = 00000b; Port2 = 00001b • P1/2_PHYMODE 2..0 see PHY_CONFIG in the SYSTEM-CONTROL register area • P1/2_MIIMODE 1..0 MII-Interface (permanently set) • P1/2_SMIISOURCESYNC Normal SMII-Mode • P1/2_FXMODE see PHY_CONFIG in the SYSTEM-CONTROL register area • P1/2_AUTOMIDIXEN ...
Page 93 - 0 Memory Description; Memory Partitioning of the ERTEC 200
10 Memory Description This section presents a detailed description of the memory areas of all integrated function groups. 10.1 Memory Partitioning of the ERTEC 200 The table below lists the AHB masters along with their options for accessing various memory areas. Start- and Endadress Seg. Function Ar...
Page 94 - Detailed Memory Description; IO Bank 0
10.2 Detailed Memory Description The table below presents a detailed description of the memory segments. Mirrored segments should not be used for addressing to ensure compatible memory expansion at a later date. Segment Contents Größe Adressbereich Beschreibung 0 Boot-ROM (0-8kB) or EMIF-SDRAM (0-12...
Page 96 - 1 Test and Debugging; ETM9 Embedded Trace Macrocell; Modes; Section 9; Registers
11 Test and Debugging 11.1 ETM9 Embedded Trace Macrocell An ETM9 module is integrated in the ARM946E-S of the ERTEC 200 to enable the instruction code and data to be traced. The ARM946E-S supplies the ETM module with the signals needed to carry out the trace functions. The ETM9 module is operated by...
Page 97 - Debugging via UART
11.2 Trace Interface The trace interface is parameterized, enabled, and disabled by means of a connected debugger (e.g. by Lauterbach) on the JTAG interface. A Trace port is provided in the ERTEC 200 for tracing internal processor states: • PIPESTA [2:0] • TRACESYNC • TRACECLK • TRACEPKT[7:0] The PI...
Page 98 - 2 Miscellaneous
12 Miscellaneous 12.1 Acronyms/Glossary: AHB AMBA A dvanced H igh Performance B us (Multimaster, Bursts) AMBA A dvanced M icrocontroller B us A rchitecture APB AMBA A dvanced P eripheral B us (Single master, bursts) BIST B uilt I n S elf T est ComDeC Com munication, De velopment & C ertification...
Page 99 - ARM Prime Cell; Embedded Trace Macrocell
12.2 References: /1/ Technical Reference Manual ARM946E-S REV1 16 February 2001 (DDI 0201A_946ES.PDF); /2/ Technical Reference Manual ARM946E-S 16 December 1999 (DDI_ 0165A_9E-S_TRM. PDF); /3/ AHB PCI Bridge Revision2.5 08 July 2002 (amba2pci_rev2.5.pdf); /4/ AMBA Specification (Revision 2.0), 1999;...
