Page 4 - Semiconductor Group; Contents
80C517A/83C517A-5 Semiconductor Group Contents Page 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 2 Fundamental Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 3 Memory Organization . . ....
Page 5 - Introduction
Semiconductor Group 1 - 1 1 Introduction The SAB 80C517A is a superset of the high end microcontroller SAB 80C517. Whil e maintaining all architectural and operational charac teristi cs of the SAB 80C517 theSAB 80C517A incorporates more on-chip RAM as well as some enhancements in the compare /captur...
Page 6 - Package
Semiconductor Group 1 - 2 Listed below is a summary of the main features of the SAB 80C517A: The pin functions of the SAB 80C517A are identical with those of the SAB 80C517/80C537 with oneexception: Package SAB 80C517A SAB 80C517 / 80C537 PLCC-84/60 PMRFP-100/72 HWPD V SS ● SAB 80C517A/83C517A-5, up...
Page 7 - Fundamental Structure
Semiconductor Group 2 - 1 2 Fundamental Structure The SAB 80C517A/83C517A-5 is a high-end member of the Siemens SAB 8051 family of microcontrollers. It is designed in Siemens ACMOS technology and based on the SAB 8051architecture. ACMOS is a technology which combines high-speed and density character...
Page 9 - Memory Organization
Semiconductor Group 3 - 1 Memory Organization 3 Memory Organization According to the SAB 8051 architecture, the SAB 80C517A has separate address spaces forprogram and data memory. Figure 3-1 illustrates the mapping of address spaces. Figure 3-1Memory Map
Page 10 - Program Memory, ROM Protection
Semiconductor Group 3 - 2 Memory Organization 3.1 Program Memory, ROM Protection The SAB 83C517A-5 has 32 Kbyte of on-chip ROM, while the SAB 80C517A has no internal ROM. The program memory can externally be expanded up to 64 Kbyte. Pin EA controls whetherprogram fetches below address 8000H are done...
Page 11 - Data Memory; – External Data Memory
Semiconductor Group 3 - 3 Memory Organization 3.2 Data Memory The data memory space consists of an internal and an external memory space. The SAB 80C517Acontains another 2 kByte of On-Chip RAM above the 256 Bytes internal RAM of the base typeSAB 80C517. This RAM is called XRAM in this document. – Ex...
Page 14 - Block; XRAM
Semiconductor Group 3 - 6 Memory Organization Table 3-1, Special Function Register (cont´d) 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) X means that the value is indeterminate Bl...
Page 16 - Table 3-1, Special Function Register
Semiconductor Group 3 - 8 Memory Organization Table 3-1, Special Function Register 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) X means that the value is indeterminate Block Symbo...
Page 17 - Architecture for the XRAM; MOVX
Semiconductor Group 3 - 9 Memory Organization 3.4 Architecture for the XRAM The contents of the XRAM is not affected by a reset or HW Power Down. After power-up thecontents is undefined, while it remains unchanged during and after a reset or HW Power Down ifthe power supply is not turned off. The ad...
Page 18 - Accesses to XRAM using the Registers R0/R1
Semiconductor Group 3 - 10 Memory Organization Accesses to XRAM using the Registers R0/R1 The 8051 architecture provides also instructions for access to external data memory range whichuse only an 8-bit address (indirect addressing with registers R0 or R1). The instructions are: MOVX A, @ Ri (Read) ...
Page 21 - P2 still shows 0AAH but XRAM is addressed
Semiconductor Group 3 - 13 Memory Organization Figure 3-4Use of Port 2 as I/O-Port At a write to Port 2, XRAM address in XPAGE-register will be overwritten because of the concurrentwrite to Port 2 and XPAGE-register. So whenever XRAM is used and the XRAM address differsfrom the byte written to Port ...
Page 23 - Special Function Register SYSCON; Reset value of SYSCON is XXXX XX01B.; Bit; MSB
Semiconductor Group 3 - 15 Memory Organization 3.4.2 Control of XRAM in the SAB 80C517A There are two control bits in register SYSCON which control the use and the bus operation duringaccesses to the additional On-Chip RAM in XDATA range ( XRAM). Special Function Register SYSCON Reset value of SYSCO...
Page 24 - a) Use of P0 and P2 pins during the MOVX access.
Semiconductor Group 3 - 16 Memory Organization A hardware protection is done by an unsymetric latch at XMAP0-bit. A unintentional disabling ofXRAM could be dangerous since indeterminate values could be read from external bus. To avoidthis the XMAP-bit is forced to ’1’ only by reset. Additional durin...
Page 26 - The function of the new Hardware Power Down Mode is as follows:; System Reset
Semiconductor Group 4 - 1 4 System Reset 4.1 Additional Hardware Power Down Mode in the SAB 80C517A The SAB 80C517A has an additional Power Down Mode which can be initiated by an external signalat a dedicated pin. This pin is labeled HWPD and is a floating input line (active low). This pinsubstitute...
Page 29 - Hardware Power Down Reset Timing; Delay time caused by internal logic is not included.
Semiconductor Group 4 - 4 4.2 Hardware Power Down Reset Timing Following figures are showing the timing diagrams for entering (figure 4-1) and leaving (figure 4-2)the Hardware Power Down Mode. If there is only a short signal at pin HWPD (i.e. HWPD is sampledactive only once), then a complete interna...
Page 33 - Fast internal Reset after Power-On
Semiconductor Group 4 - 8 4.3 Fast internal Reset after Power-On The SAB 80C517A can use the oscillator watchdog unit for a fast internal reset procedure afterpower-on. Figure 4-4 shows the power-on sequence under control of the oscillator watchdog. Normally the devices of the 8051 family (like the ...
Page 36 - On-Chip Peripheral Components
Semiconductor Group 5 - 1 On-Chip Peripheral Components 5 On-Chip Peripheral Components 5.1 Digital I/O Port Circuitry To realize the Hardware Power Down Mode with floating Port pins in the SAB 80C517A/83C517A 5the standard port structure used in the 8051 Family is modified ( figure 5-1). The FETs p...
Page 38 - The table 5-1 below shows the sample time; and the conversion time; and the selected prescaler (see also Bit ADCL in SFR ADCON 1).; Prescaler
Semiconductor Group 5 - 3 On-Chip Peripheral Components 5.2 10-bit A/D-Converter In the SAB 80C517A is a new high performance / high speed 12-channel 10-bit A/D-Converter isimplemented. Its successive approximation techniqe provides 7 µ s conversion time ( f OSC =16 MHz). The conversion principle is...
Page 40 - Special Function Registers ADCON0, ADCON1
Semiconductor Group 5 - 5 On-Chip Peripheral Components Special Function Registers ADCON0, ADCON1 The reset value of ADCON0 and ADCON1 is 00H Bit Function ADEX Internal / external start of conversion.When set, the external start of conversion by P6.0 / ADST is enabled. BSY Busy flag.This flag indica...
Page 41 - Special Function Register ADDATH, ADDATL
Semiconductor Group 5 - 6 On-Chip Peripheral Components Special Function Register ADDATH, ADDATL The reset value of ADDATH and ADDATL is 00H.The registers ADDATH (0D9H) and ADDATL (0DAH) contain the 10-bit conversion result. The datais read as two 8-bit bytes. Data is presented in left justified for...
Page 43 - Additional Compare Mode for the Concurrent Compare Unit
Semiconductor Group 5 - 8 On-Chip Peripheral Components 5.3 Additional Compare Mode for the Concurrent Compare Unit The SAB 80C517A has an additional compare mode (compare mode 2) in the Compare/CaptureUnit which can be used for the Concurrent Compare Output at P5. In this compare mode 2 the P5pins ...
Page 45 - Special Function Register CC4EN
Semiconductor Group 5 - 10 On-Chip Peripheral Components Special Function Register CC4EN The reset value of SFR CC4EN is 00H. Bit Function COCON2COCON1COCON0 Selects number of compare outputs at P5 (for compare modes 1 and 2); see table 2-2 COCAH4COCAL4 0 0 0 1 1 0 1 1 Compare/capture mode for regis...
Page 46 - COCOEN1 COCOEN0
Semiconductor Group 5 - 11 On-Chip Peripheral Components Table 5-3, Configurations for Concurrent Compare Mode and Compare Mode 2 at P5 The other combinations are reserved and must not be used. COCAH4 COCAL4 COCOEN1 COCOEN0 Function of CC4 Function of Compare Modes at P5 0 0 0 0 0 0 1 0 Compare / Ca...
Page 48 - Extended Prescaler for Timer 2; option there are now scale ratings of; Prescaler Ratio
Semiconductor Group 5 - 13 On-Chip Peripheral Components Extended Prescaler for Timer 2 The prescaler for Timer 2 has an extended range. This prescaler divides the input clock for Timer 2when it is operated in timer mode. In addition to the ÷ 2 option there are now scale ratings of ÷ 4 and ÷ 8 avail...
Page 49 - New Baud Rate Generators for Serial Channel 0 and Serial Channel 1; /2 input frequency. On overflow of this timer there is an
Semiconductor Group 5 - 14 On-Chip Peripheral Components 5.4 New Baud Rate Generators for Serial Channel 0 and Serial Channel 1 5.4.1 Serial Channel 0 Baud Rate Generator The Serial Channel 0 has a new baud rate generator which provides greater flexibility and betterresolution. It substitutes the 80...
Page 50 - Special Function Register S0RELH, S0RELL
Semiconductor Group 5 - 15 On-Chip Peripheral Components Special Function Register S0RELH, S0RELL Reset value of S0RELL is 0D9H, S0RELH contains XXXX XXX11B. Bit Function S0RELH.0-1 Reload value. Upper two bits of the timer reload value. S0RELL.0-7 Reload value. Lower 8 bit of timer reload value. 7 ...
Page 51 - x oscillator frequency
Semiconductor Group 5 - 16 On-Chip Peripheral Components Figure 5-5 shows a block diagram of the options available for baud rate generation of SerialChannel 0. It is a fully compatible superset of the functionality of the SAB 80C517. The new baudrate generator can be used in modes 1 and 3 of the Ser...
Page 52 - Serial Channel 1 Baud Rate Generator; /2 input frequency. On overflow of this timer there is an automatic
Semiconductor Group 5 - 17 On-Chip Peripheral Components 5.4.2 Serial Channel 1 Baud Rate Generator A new baud rate generator for Serial Channel 1 now offers a wider range of selectable baud rates.Especially a baud rate of 1200 baud can be achieved now. The baud rate generator itself is identical wi...
Page 53 - Special Function Register SRELH, SRELL
Semiconductor Group 5 - 18 On-Chip Peripheral Components Special Function Register SRELH, SRELL Reset value of S1RELL is 00H, S1RELH contains XXXX XXX11B. Bit Function S1RELH.0-1 Reload value. Upper two bits of the timer reload value. S1RELL.0-7 Reload value. Lower 8 bit of timer reload value. 7 6 5...
Page 54 - Modified Oscillator Watchdog Unit; The unit serves three functions:
Semiconductor Group 5 - 19 On-Chip Peripheral Components 5.5 Modified Oscillator Watchdog Unit The SAB 80C517A has a new oscillator watchdog unit that has an improved functionality withrespect to the SAB 80C517’s oscillator watchdog. Use of the Oscillator Watchdog Unit The unit serves three function...
Page 55 - Detailled Description of the Oscillator Watchdog Unit
Semiconductor Group 5 - 20 On-Chip Peripheral Components Detailled Description of the Oscillator Watchdog Unit Figure 5-7 shows the block diagram of the oscillator watchdog unit. It consists of an internal RCoscillator which provides the reference frequency for the comparison with the frequency of t...
Page 57 - Interrupt System
Semiconductor Group 6 - 1 6 Interrupt System 6.1 Additional Interrupt for Compare Registers CM0 to CM7 There is an additional interrupt which is vectored to on a compare match in one of the eightcomparators of the compare registers CM0 to CM7, when compare mode 1 is selected for thecorresponding cha...
Page 59 - Special Function Register IRCON1; The reset value of IRCON1 is 00H.; ICMPx
Semiconductor Group 6 - 3 Special Function Register IRCON1 The reset value of IRCON1 is 00H. Bit Function ICMPx Compare x interrupt request flag. Set by hardware when a compare match in compare mode 1 with compare register CMx occured (only, if compare function enabled for CMx). ICMPx must be cleare...
Page 60 - Interrupt Structure; The new interrupt sources are:
Semiconductor Group 6 - 4 6.2 Interrupt Structure This section summarizes the expanded interrupt structure of the SAB 80C517A which has 3 newinterrupt vectors in addition to the 14 vectors of the SAB 80C517. Thus, 17 vectors are availablenow. The new interrupt sources are: 1. Request Flags ICMP0 to ...
Page 63 - Device Specification; Preliminary
Device Specification 7-1 05.94 4 De vice Specific ation High-Performance SAB 80C517A/83C517A-5 8-Bit CMOS Single-Chip Microcontroller Preliminary SAB 83C517A-5 Microcontroller with factory mask-programmable ROM SAB 80C517A Microcontroller for external ROM ● SAB 80C517A/83C517A-5, ● Eight data pointe...
Page 64 - Ordering Information
Device Specification Semiconductor Group 7-2 Ordering Information Type Ordering code Package Description8-bit CMOS microcontroller SAB 80C517A-N18 Q67120-C583 P-LCC-84 for external memory,18 MHz SAB 80C517A-M18 TBD P-MRFP-100 SAB 83C517A-5N18 Q67120-C582 P-LCC-84 with mask-programmable ROM, 18 MHz S...
Page 65 - Logic Symbol
Device Specification Semiconductor Group 7-3 Logic Symbol
Page 66 - Typ; HWPD
Device Specification Semiconductor Group 7-4 The pin functions of the SAB 80C517A are identical with those of the SAB 80C517/80C537 with one exception: Typ SAB 80C517A SAB 80C517/80C537 P-LCC-84, Pin 60 HWPD N.C. P-MQFP-100-2,Pin 36 Pin Configuration(P-LCC-84)
Page 68 - Pin Definitions and Functions
Device Specification Semiconductor Group 7-6 Pin Definitions and Functions Symbol Pin Number I/O *) Function P-LCC-84 P-MQFP-100-2 P4.0 – P4.7 1– 3, 5 – 9 64 - 66,68 - 72 I/O Port 4is a bidirectional I/O port with internalpull-up resistors. Port 4 pins that have 1s written to them are pulled high by...
Page 69 - Symbol; RESET
Device Specification Semiconductor Group 7-7 Pin Definitions and Functions (cont’d) Symbol Pin Number I/O *) Function P-LCC-84 P-MQFP-100-2 RESET 10 73 I RESETA low level on this pin for the duration of one machine cycle while the oscillator is running resets the SAB 80C517A. A small internal pull-u...
Page 74 - concurrent compare or Set/Reset
Device Specification Semiconductor Group 7-12 HWPD 60 36 I Hardware Power DownA low level on this pin for the duration of one machine cycle while the oscillator is running resets the SAB 80C517A. A low level for a longer period will force the part to Power Down Mode with the pins floating. (see tabl...
Page 75 - of serial interface 1
Device Specification Semiconductor Group 7-13 P6.0 - P6.7 70 - 77 46 - 50,54 - 56 I/O Port 6is a bidirectional I/O port with internal pull-up resistors. Port 6 pins that have 1 s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, po...
Page 76 - Circuit ground potential; Not connected
Device Specification Semiconductor Group 7-14 Pin Definitions and Functions (cont’d) Symbol Pin Number I/O *) Function P-LCC-84 P-MQFP-100-2 RO 82 61 O Reset OutputThis pin outputs the internally synchronized reset request signal. This signal may be generated by an external hardware reset, a watchdo...
Page 78 - Functional Description
Device Specification Semiconductor Group 7-16 Functional Description The SAB 80C517A is based on 8051 architecture. It is a fully compatible member of the Siemens SAB 8051/80C51 microcontroller family being an significantly enhanced SAB 80C517. The SAB 80C517A is therefore compatible with code writt...
Page 79 - Restrictions; yes
Device Specification Semiconductor Group 7-17 Program Memory (’Code Space’) The SAB 83C517A-5 has 32 Kbyte of on-chip ROM, while the SAB 80C517A has no internal ROM. The program memory can externally be expanded up to 64 Kbyte. Pin EA controls whether program fetches below address 8000H are done fro...
Page 80 - External Data Memory
Device Specification Semiconductor Group 7-18 Data Memory (’Code Space’) The data memory space consists of an internal and an external memory space. The SAB 80C517A contains another 2 Kbyte on On-Chip RAM above the 256-bytes internal RAM of the base type SAB 80C517. This RAM is called XRAM in this d...
Page 81 - Accesses to XRAM
Device Specification Semiconductor Group 7-19 Accesses to XRAM Because the XRAM is used in the same way as external data memory the same instruction types must be used for accessing the XRAM. Note: If a reset occurs during a write operation to XRAM, the effect on XRAM depends on the cycle which the ...
Page 82 - Special Function Register XPAGE
Device Specification Semiconductor Group 7-20 Special Function Register XPAGE The reset value of XPAGE is 00 H . XPAGE can be set and read by software. The register XPAGE provides the upper address byte for accesses to XRAM with MOVX @Ri instructions. If the address formed from XPAGE and Ri is less ...
Page 83 - Control of XRAM in the SAB 80C517A; Reset value of SYSCON is xxxx xx01B.
Device Specification Semiconductor Group 7-21 Control of XRAM in the SAB 80C517A There are two control bits in register SYSCON which control the use and the bus operation during accesses to the additional On-Chip RAM (XRAM). Special Function Register SYSCON Reset value of SYSCON is xxxx xx01B. The c...
Page 85 - haviour of P0/P2 and; RD; during MOV
Device Specification Semiconductor Group 7-23 s 00 10 X1 DPTR < XRAM ad dres s ran g e MO VX @Ri MO VX @D P T R a) P0/P2 ➝ Bus b) RD / WR ac ti ve c ) ex t. m e m o ry is us ed a) P0 /P2 ➝ Bus b) RD / WR ac tiv e c ) ex t. me mo ry i s u s e d a) P0/P2 ➝ Bus b) R D / WR ac ti v e c) ex t. me m o ...
Page 86 - Multiple Datapointers
Device Specification Semiconductor Group 7-24 Multiple Datapointers As a functional enhancement to standard 8051 controllers, the SAB 80C517A contains eight 16-bit datapointers. The instruction set uses just one of these datapointers at a time. The selection of the actual datapointer is done in spec...
Page 89 - Address
Device Specification Semiconductor Group 7-27 Table 2Special Function Register (cont’d) Address Register Contentsafter Reset Address Register Contentsafter Reset F0 H F1 H F2 H F3 H F4 H F5 H F6 H F7 H B 1) reservedCML6CMH6CML7 CMH7 CMENCMSEL 00 H XX H 00 H 00 H 00 H 00 H 00 H 00 H F8 H F9 H FA H FB...
Page 94 - The table below shows the sample time; Sample Time
Device Specification Semiconductor Group 7-32 A/D Converter In the SAB 80C517A a new high performance / high-speed 12-channel 10-bit A/D-Converter is implemented. Its successive approximation technique provides 7 µ s con-version time ( f OSC = 16 MHz). The conversion principle is upward compatible t...
Page 97 - Assigned Timer Compare Register; Timer 2
Device Specification Semiconductor Group 7-35 Table 4CCU Compare Configuration Assigned Timer Compare Register Compare Output Possible Modes Timer 2 CRCH/CRCLCC1H/CC1LCC2H/CC2LCC3H/CC3LCC4H/CC4L CC4H/CC4L : CC4H/CC4L COMSETL/COMSETH COMCLRL/COMCLRH CM0H/CM0L : CM7H/CM7L P1.0/INT3/CC0P1.1/INT4/CC1P1....
Page 99 - Compare; A timer overflow signal does not affect the compare-output.; Capture
Device Specification Semiconductor Group 7-37 Compare In compare mode, the 16-bit values stored in the dedicated compare registers are compared to the contents of the timer 2 register or the compare timer register. If the count value in the timer registers matches one of the stored value, an appropr...
Page 100 - Reload of Timer 2; timer/counter 1 in this mode holds its count.
Device Specification Semiconductor Group 7-38 Reload of Timer 2 A 16-bit reload can be performed with the 16-bit CRC register, which is a concatenation of the 8-bit registers CRCL and CRCH. There are two modes from which to select: Mode 0: Reload is caused by a timer overflow (auto-reload). Mode 1: ...
Page 109 - Abbreviations
Device Specification Semiconductor Group 7-47 Table 6Performing a MDU-Calculation Table 7Shift Operation with the MDU Abbreviations D’end : Dividend, 1st operand of division D’or : Divisor, 2nd operand of division M’and : Multiplicand, 1st operand of multiplication M’or : Multiplicator, 2nd operand ...
Page 110 - ) the port can also be used as digital input port.
Device Specification Semiconductor Group 7-48 with internal pull-up resistors. That means, when configured as inputs, ports 1 to 6 will be pulled high and will source current when externally pulled low. Port 0 will float when configured as input. Port 0 and port 2 can be used to expand the program a...
Page 111 - Power Saving Modes
Device Specification Semiconductor Group 7-49 Power Saving Modes The SAB 80C517A provides – due to Siemens ACMOS technology – four modes in which pow-er consumption can be significantly reduced. – The Slow Down Mode The controller keeps up the full operating functionality, but is driven with one eig...
Page 112 - Requirements for Hardware Power Down Mode; The slow down mode is disabled by clearing bit SD.; Idle Mode; There are two ways to terminate the idle mode:
Device Specification Semiconductor Group 7-50 Requirements for Hardware Power Down Mode There is no dedicated pin to enable the Hardware Power Down Mode. Nevertheless for a correct function of the Hardware Power Down Mode the oscillator watchdog unit including its internal RC oscillator is needed. T...
Page 113 - Termination of HWPD Mode:; Termination of HWPD Mode:
Device Specification Semiconductor Group 7-51 Power Down Mode The power down mode is entered by two consecutive instructions directly following each other. The first instruction has to set the flag PDE (power down enable) and must not set PDS (power down set). The following instruction has to set th...
Page 117 - Serial Interface 0; Serial Interface 0 can operate in 4 modes:; Variable Baud Rates for Serial Interface 0
Device Specification Semiconductor Group 7-55 Serial Interface 0 Serial Interface 0 can operate in 4 modes: Mode 0: Shift register mode:Serial data enters and exits through R × D0. T × D0 outputs the shift clock 8 data bits are transmitted/received (LSB first). The baud rate is fixed at 1/12 of the ...
Page 118 - Serial Interface 1; Serial interface 1 can operate in two asynchronous modes:; Variable Baud Rates for Serial Interface 1.; ) is generated by an 10-bit free running timer
Device Specification Semiconductor Group 7-56 Serial Interface 1 Serial interface 1 can operate in two asynchronous modes: Mode A: 9-bit UART, variable baud rate.11 bits are transmitted (through T × D1) or received (through R × D1): a start bit (0), 8 data bits (LSB first), a programmable 9th, and a...
Page 119 - Watchdog Units; The WDT can be activated by hardware or software.
Device Specification Semiconductor Group 7-57 Watchdog Units The SAB 80C517A offers two enhanced fail safe mechanisms, which allow an automatic recovery from hardware failure or software upset: – programmable watchdog timer (WDT), variable from 512 µ s up to appr. 1.1 s time-out period @12 MHz. Upwa...
Page 120 - Oscillator Watchdog
Device Specification Semiconductor Group 7-58 Oscillator Watchdog The unit serves three functions: – Monitoring of the on-chip oscillator’s function. The watchdog supervises the on-chip oscillator’s frequency; if it is lower than the frequency of the auxiliary RC oscillator in the watchdog unit, the...
Page 122 - Fast internal reset after power-on; Delay time between power-on and correct reset state:; Instruction Set; Microcontroller Family SAB 8051 Pocket Guide
Device Specification Semiconductor Group 7-60 Fast internal reset after power-on The SAB 80C517A can use the oscillator watchdog unit for a fast internal reset procedure after power-on. Normally members of the 8051 family (like the SAB 80C517) enter their default reset state not before the on-chip o...
Page 124 - Parameter
Device Specification Semiconductor Group 7-62 DC Characteristics (cont’d) Parameter Symbol Limit Values Unit Test condition min. max. Output low voltage (ports 1, 2, 3, 4, 5, 6) V OL – 0.45 V I OL =1.6 mA 1) Output low voltage (ports ALE, PSEN, RO) V OL1 – 0.45 V I OL =3.2 mA 1) Output high voltage ...
Page 127 - CLCL
Device Specification Semiconductor Group 7-65 AC Characteristics V CC = 5 V + 10 %, – 15 %; V SS = 0 V T A = 0 to 70 o C for the SAB 80C517A/83C517A-5 T A = – 40 to 85 o C for the SAB 80C517A-T3/83C517A-5-T3 T A = – 40 to110 o C for the SAB 80C517A-T4/83C517A-5-T4 ( C L for port 0, ALE and PSEN outp...
Page 129 - Program Memory Read Cycle
Device Specification Semiconductor Group 7-67 Program Memory Read Cycle Data Memory Read Cycle MCT00096 ALE PSEN Port 2 LHLL t A8 - A15 A8 - A15 A0 - A7 Instr.IN A0 - A7 Port 0 t AVLL PLPH t t LLPL t LLIV t PLIV t AZPL t LLAX t PXIZ t PXIX t AVIV t PXAV
Page 130 - Data Memory Write Cycle
Device Specification Semiconductor Group 7-68 Data Memory Write Cycle MCT00098 ALE PSEN Port 2 WHLH t Port 0 WR t WLWH t LLWL t QVWX t AVLL t LLAX2 t QVWH t AVWL t WHQX A0 - A7 from Ri or DPL from PCL A0 - A7 Instr.IN Data OUT A8 - A15 from PCH P2.0 - P2.7 or A8 - A15 from DPH
Page 134 - ROM Verification Mode 2
Device Specification Semiconductor Group 7-72 ROM Verification Mode 2 (New Verify Mode for Protected and not Protected ROM) ROM Verification Mode 2
Page 135 - Application Circuitry for Verifying the Internal ROM
Device Specification Semiconductor Group 7-73 Application Circuitry for Verifying the Internal ROM
Page 136 - AC Testing: Float Waveforms
Device Specification Semiconductor Group 7-74 AC Testing: Input, Output Waveforms AC Testing: Float Waveforms Recommended Oscillator Circuits AC Inputs during testing are driven at V CC - 0.5 V for a logic ’1’ and 0.45 V for a logic ’0’. Timing measure- ments are made at V IHmin for a logic ’1’ and ...
Page 137 - Package Outlines
Device Specification Semiconductor Group 7-75 Package Outlines SMD = Surface Mounted Device Dimensions in mm Dimensions in mm Plastic Package, P-MQFP-100-2 – SMD(Plastic Metric Rectangular Flat Package) Plastic Package, P-LCC-84 – SMD(Plastic Leaded Chip-Carrier)
