Maxim MAX12527 - Manual
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Table of Contents:
- Page 2 – SECLK
- Page 7 – Typical Operating Characteristics; pF at digital outputs, V
- Page 8 – DIFFERENTIAL NONLINEARITY; Typical Operating Characteristics (continued)
- Page 11 – GAIN ERROR vs. TEMPERATURE
- Page 12 – Pin Description
- Page 14 – Detailed Description; PIN; Bypass REFOUT to GND with a; Figure 1. Pipeline Architecture—Stage Blocks
- Page 15 – Figure 2. Functional Diagram
- Page 16 – common-mode voltage of V; Reference Output; to GND when the MAX12527 is powered; Reference Configurations; with a V; REFIN; REFERENCE MODE; Table 1. Reference Modes
- Page 17 – Applications Information; Clock Duty-Cycle Equalizer
- Page 18 – System Timing Requirements; Figure 4. Siimplified Clock Input Circuit; FUNCTION; Not Allowed; Figure 5. System Timing Diagram
- Page 19 – Digital Output Data and Output Format Selection
- Page 22 – Using Transformer Coupling; termination resistors provide an equivalent
- Page 24 – Board Layout; Figure 13. External Unbuffered Reference Driving Multiple ADCs
- Page 25 – mount devices for minimum inductance. Bypass V; to; to GND with a 220μF ceramic; Parameter Definitions; Electrical Characteristics; Offset Error; RMS
- Page 26 – Aperture Jitter; AJ; Aperture Delay; OUT; Overdrive Recovery Time; THD
- Page 27 – THIN QFN; Pin Configuration
- Page 28 – Package Information
General Description
The MAX12527 is a dual 3.3V, 12-bit analog-to-digital
converter (ADC) featuring fully differential wideband
track-and-hold (T/H) inputs, driving internal quantizers.
The MAX12527 is optimized for low power, small size,
and high dynamic performance in intermediate frequen-
cy (IF) and baseband sampling applications. This dual
ADC operates from a single 3.3V supply, consuming
only 620mW while delivering a typical 69.8dB signal-to-
noise ratio (SNR) performance at a 175MHz input fre-
quency. The T/H input stages accept single-ended or
differential inputs up to 400MHz. In addition to low oper-
ating power, the MAX12527 features a 166µW power-
down mode to conserve power during idle periods.
A flexible reference structure allows the MAX12527 to
use the internal 2.048V bandgap reference or accept
an externally applied reference and allows the refer-
ence to be shared between the two ADCs. The refer-
ence structure allows the full-scale analog input range
to be adjusted from ±0.35V to ±1.15V. The MAX12527
provides a common-mode reference to simplify design
and reduce external component count in differential
analog input circuits.
The MAX12527 supports either a single-ended or differ-
ential input clock. User-selectable divide-by-two (DIV2)
and divide-by-four (DIV4) modes allow for design flexibil-
ity and help eliminate the negative effects of clock jitter.
Wide variations in the clock duty cycle are compensated
with the ADC’s internal duty-cycle equalizer (DCE).
T h e M A X 1 2 5 2 7 f e a t u r e s t w o p a r a l l e l , 1 2 - b i t - w i d e ,
CMOS-compatible outputs. The digital output format is
pin-selectable to be either two’s complement or Gray
code. A separate power-supply input for the digital out-
puts accepts a 1.7V to 3.6V voltage for flexible interfac-
ing with various logic levels. The MAX12527 is available
in a 10mm x 10mm x 0.8mm, 68-pin thin QFN package
with exposed paddle (EP), and is specified for the
extended (-40
°
C to +85
°
C) temperature range.
For a 14-bit, pin-compatible version of this ADC, refer to
the MAX12557 data sheet.
Applications
IF and Baseband Communication Receivers
Cellular, LMDS, Point-to-Point Microwave,
MMDS, HFC, WLAN
I/Q Receivers
Ultrasound and Medical Imaging
Portable Instrumentation
Digital Set-Top Boxes
Low-Power Data Acquisition
Features
♦
Direct IF Sampling Up to 400MHz
♦
Excellent Dynamic Performance
70.4dB/69.8dB SNR at f
IN
= 70MHz/175MHz
84.4dBc/80.2dBc SFDR at f
IN
= 70MHz/175MHz
♦
3.3V Low Power Operation
647mW (Differential Clock Mode)
620mW (Single-Ended Clock Mode)
♦
Fully Differential or Single-Ended Analog Input
♦
Adjustable Differential Analog Input Voltage
♦
750MHz Input Bandwidth
♦
Adjustable, Internal or External, Shared Reference
♦
Differential or Single-Ended Clock
♦
Accepts 25% to 75% Clock Duty Cycle
♦
User-Selectable DIV2 and DIV4 Clock Modes
♦
Power-Down Mode
♦
CMOS Outputs in Two’s Complement or Gray
Code
♦
Out-of-Range and Data-Valid Indicators
♦
Small, 68-Pin Thin QFN Package
♦
14-Bit Compatible Version Available (MAX12557)
♦
Evaluation Kit Available (Order MAX125
2
7 EV Kit)
MAX12527
Dual, 65Msps, 12-Bit, IF/Baseband ADC
________________________________________________________________
Maxim Integrated Products
1
Ordering Information
19-3543; Rev 0; 2/05
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
PART
TEMP RANGE
PIN-PACKAGE
MAX12527ETK
-40
°
C to +85
°
C
68 Thin QFN-EP*
(10mm x 10mm x 0.8mm)
Pin Configuration appears at end of data sheet.
*
EP = Exposed paddle.
PART
SAMPLING RATE
(Msps)
RESOLUTION
(Bits)
MAX12557
65
14
MAX12527
65
12
Selector Guide
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Summary
MAX12527 Dual, 65Msps, 12-Bit, IF/Baseband ADC 2 _______________________________________________________________________________________ ABSOLUTE MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS (V DD = 3.3V, OV DD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), C L ≈ 10pF at digital outputs, V IN =...
MAX12527 Dual, 65Msps, 12-Bit, IF/Baseband ADC _______________________________________________________________________________________ 7 ELECTRICAL CHARACTERISTICS (continued) (V DD = 3.3V, OV DD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), C L ≈ 10pF at digital outputs, V IN = -0.5dBFS (di...
MAX12527 Dual, 65Msps, 12-Bit, IF/Baseband ADC 8 _______________________________________________________________________________________ INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE MAX12527 toc07 DIGITAL OUTPUT CODE INL (LSB) 3600 3000 1800 2400 1200 600 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -...
