Maxim DS21Q55 - Manual

Maxim DS21Q55

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Table of Contents:

  • Page 2 – Please contact
  • Page 4 – FEATURE HIGHLIGHTS
  • Page 8 – TABLE OF CONTENTS
  • Page 11 – OPERATING PARAMETERS; MECHANICAL DESCRIPTIONS
  • Page 12 – DOCUMENT REVISION HISTORY; Initial Preliminary Release
  • Page 13 – BLOCK DIAGRAM
  • Page 14 – PIN FUNCTION DESCRIPTION
  • Page 18 – Parallel Control Port Pins
  • Page 20 – JTAG Test Access Port Pins
  • Page 21 – Line Interface Pins
  • Page 23 – PIN
  • Page 30 – Register Map; REGISTER MAP SORTED BY ADDRESS; ADDRESS
  • Page 36 – SPECIAL PER-CHANNEL REGISTER OPERATION; PCPR
  • Page 37 – PCDR1
  • Page 38 – PROGRAMMING MODEL; Issue Reset
  • Page 39 – MSTRREG
  • Page 40 – Interrupt Handling; ESIB; Status Registers
  • Page 41 – Information Registers; Interrupt Information Register 1
  • Page 42 – CLOCK MAP; TRANSMIT CLOCK SOURCE
  • Page 43 – T1 FRAMER/FORMATTER CONTROL REGISTERS; T1 Receive Control Register 1
  • Page 44 – T1 Receive Control Register 2
  • Page 45 – T1 Transmit Control Register 1
  • Page 46 – T1 Transmit Control Register 2
  • Page 47 – T1 Common Control Register 1
  • Page 48 – T1 Transmit Transparency
  • Page 49 – T1 Receive Digital Milliwatt Enable Register 1
  • Page 50 – T1 Information Register; Information Register 1
  • Page 51 – T1 ALARM CRITERIA; ALARM; Blue Alarm
  • Page 52 – E1 FRAMER/FORMATTER CONTROL REGISTERS; E1 Receive Control Register 1
  • Page 53 – E1 SYNC/RESYNC CRITERIA; FRAME OR; FAS; E1 Receive Control Register 2
  • Page 54 – E1 Transmit Control Register 1
  • Page 55 – E1 Transmit Control Register 2
  • Page 56 – Automatic Alarm Generation; enabled at the same time.
  • Page 57 – E1 Information Registers; Information Register 3
  • Page 58 – E1 ALARM CRITERIA; An
  • Page 59 – COMMON CONTROL AND STATUS REGISTERS; Common Control Register 1
  • Page 60 – IDR
  • Page 61 – Interrupt Mask Re gister 2
  • Page 62 – Status Register 3
  • Page 63 – Interrupt Mask Register 3
  • Page 64 – Status Register 4
  • Page 65 – Interrupt Mask Register 4
  • Page 66 – I/O Configuration Register 1
  • Page 67 – I/O Configuration Register 2
  • Page 68 – LOOPBACK CONFIGURATION; LBCR
  • Page 70 – Per-Channel Loopback Enable Register 1
  • Page 71 – Per-Channel Loopback Enable Register 3
  • Page 72 – ERROR COUNT REGISTERS; Note; ERCNT
  • Page 73 – T1 Operation; T1 LINE CODE VIOLATION COUNTING OPTIONS; COUNT EXCESSIVE; E1 LINE CODE VIOLATION COUNTING OPTIONS; E1 CODE VIOLATION SELECT
  • Page 74 – Line Code Violation Count Register 1
  • Page 75 – T1 PATH CODE VIOLATION COUNTING ARRANGEMENTS; FRAMING MODE
  • Page 76 – Path Code Violation Count Register 1; T1 FRAMES OUT OF SYNC COUNTING ARRANGEMENTS
  • Page 78 – Frames Out Of Sync Count Register 1
  • Page 79 – DS0 MONITORING FUNCTION; TDS0SEL
  • Page 80 – Receive DS0 Monitor Registers; RDS0SEL
  • Page 81 – SIGNALING OPERATION
  • Page 83 – SIGCR; must be set to zero for proper operation.
  • Page 85 – Receive Signaling Registers
  • Page 87 – Transmit Signaling
  • Page 88 – TIME SLOT NUMBERING SCHEMES; TS
  • Page 89 – Transmit Signaling Registers
  • Page 93 – Software Signaling Insertion Enable Registers, E1 CAS Mode; Software Signaling Insertion Enable 1
  • Page 94 – SSIE3
  • Page 95 – Software Signaling Insertion Enable Registers, T1 Mode
  • Page 97 – IDLE CODE ARRAY ADDRESS MAPPING; BITS 0–5 OF IAAR REGISTER
  • Page 98 – Idle Code Programming Examples; The following example sets all transmit idle codes to 7Eh:
  • Page 101 – Transmit Channel Idle Code Enable Register
  • Page 102 – Receive Ch annel Idle Code Enable Register 3
  • Page 103 – CHANNEL BLOCKING REGISTERS; Fractional T1/E1 Support; Receive Channel Blocking Register 1
  • Page 104 – Receive Channel Blocking Register 3
  • Page 105 – Transmit Channel Blocking Register 3
  • Page 106 – ELASTIC STORES OPERATION; Interleaved PCM Bus Operation.
  • Page 107 – ESCR
  • Page 108 – Status Register 5
  • Page 111 – Elastic Stores Initialization; INITIALIZATION
  • Page 113 – CRC-4 RECALCULATE METHOD
  • Page 115 – BOCC
  • Page 116 – RFDL
  • Page 117 – Interrupt Mask Register 8
  • Page 119 – RAF
  • Page 120 – T A F
  • Page 121 – Internal Register Scheme Based On CRC4 Multiframe (Method 3); RSiAF; Receive Si Bits of the Al ign Frame
  • Page 122 – RSiNAF
  • Page 123 – Receive Sa4 Bits
  • Page 124 – Receive Sa6 Bits
  • Page 125 – Receive Sa8 Bits
  • Page 126 – TSiAF; Transmit Si Bits of the Align Frame
  • Page 127 – TSiNAF
  • Page 128 – Transmit Sa4 Bits
  • Page 129 – Transmit Sa6 Bits
  • Page 130 – Transmit Sa8 Bits
  • Page 131 – TSACR
  • Page 132 – HDLC CONTROLLERS
  • Page 133 – HDLC CONTROLLER REGISTERS; NAME
  • Page 134 – HDLC Configuration
  • Page 137 – REGISTER; HxRCS1
  • Page 139 – HxTCS1
  • Page 143 – PACKET STATUS
  • Page 144 – Bits 0 to 7/Transmit FIFO Bytes Available; Receive Packet Bytes Available
  • Page 146 – Receive HDLC Code Example
  • Page 148 – TFDL
  • Page 149 – BASIC NETWORK CONNECTIONS
  • Page 151 – Receive Level Indicator and Threshold Interrupt
  • Page 152 – LIU Transmitter; register
  • Page 153 – MCLK Prescaler; CLOCK
  • Page 154 – LIU Control Registers; Line Interface Control 1
  • Page 155 – E1 Mode; APPLICATION
  • Page 157 – Line Interface Control 2
  • Page 158 – Line Interface Control 3
  • Page 160 – Information Register 2
  • Page 161 – Common Control Register 4
  • Page 162 – Status Register 1
  • Page 163 – Interrupt Mask Register 1
  • Page 164 – Recommended Circuits
  • Page 165 – PROTECTED INTERFACE USING INTERNAL RECEIVE TERMINATION; X1 and X2 are very low DCR transformers
  • Page 166 – Component Specifications; SPECIFICATION
  • Page 167 – E1 TRANSMIT PULSE TEMPLATE
  • Page 169 – E1 MODE
  • Page 170 – PROGRAMMABLE IN- BAND LOOP CODE GENERATION AND DETECTION; This function is available only in T1 mode; . To transmit a pattern, the user will load the pattern
  • Page 171 – IBCC; In-Band Code Control Register
  • Page 172 – Transmit Code Definition Register 1
  • Page 173 – Receive - Up Code Definition Register 1
  • Page 174 – Receive - Down Code Definition Register 1
  • Page 175 – Receive - Down Code Definition Register 2
  • Page 176 – Receive -Spare Code Definition Register 1
  • Page 177 – A repetitive pattern from 1 to 32 bits in length
  • Page 178 – BERT Register Description; BERT Control Register 1
  • Page 179 – BERT Control Register 2
  • Page 180 – BIC
  • Page 181 – Status Register 9
  • Page 182 – Interrupt Mask Register 9
  • Page 183 – BERT Repetitive Pattern Set
  • Page 184 – BERT Bit Counter; BERT Bit Count Register 1
  • Page 185 – BERT Error Counter; BERT Error Count Register 1
  • Page 186 – PAYLOAD ERROR INSERTION FUNCTION; Special Per-Channel Registration; TRANSMIT ERROR INSERTION SETUP SEQUENCE; STEP; or
  • Page 187 – ERC
  • Page 188 – Number Of Error Registers; VALUE; Number Of Errors 1
  • Page 189 – Number Of Errors Left Register; Number Of Errors Left 1
  • Page 190 – INTERLEAVED PCM BUS OPERATION
  • Page 191 – IBOC
  • Page 192 – IBO EXAMPLE
  • Page 193 – ESIB GROUP OF FOUR DS21Q55s
  • Page 196 – Extended System Information Bus Register 1
  • Page 197 – PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER; Common Control Register 2
  • Page 198 – Common Control Register 3
  • Page 199 – JTAG FUNCTIONAL BLOCK DIAGRAM
  • Page 200 – TAP Controller State Machine
  • Page 202 – TAP CONTROLLER STATE DIAGRAM
  • Page 203 – Instruction Register; INSTRUCTION
  • Page 204 – BYPASS; ID CODE STRUCTURE; MSB; Device ID; DEVICE ID CODES; DEVICE
  • Page 205 – Test Registers
  • Page 206 – BOUNDARY SCAN CONTROL BITS; NXA; = Not Externally Available; BIT
  • Page 208 – FUNCTIONAL TIMING DIAGRAMS
  • Page 209 – RECEIVE SIDE ESF TIMING
  • Page 210 – RECEIVE SIDE BOUNDARY TIMING (With Elastic Store Disabled); RCHBLK is programmed to block channel 24.
  • Page 211 – RECEIVE SIDE 1.544MHz BOUNDARY TIMING
  • Page 212 – RECEIVE SIDE 2.048MHz BOUNDARY TIMING (With Elastic Store Enabled); RCHBLK is forced to one in the same channels as RSER (Note 1).
  • Page 213 – TRANSMIT SIDE D4 TIMING
  • Page 214 – TRANSMIT SIDE ESF TIMING
  • Page 215 – TRANSMIT SIDE BOUNDARY TIMING (With Elastic Store Disabled); TCHBLK is programmed to block channel 2.
  • Page 216 – TRANSMIT SIDE 1.544MHz BOUNDARY TIMING
  • Page 218 – RLINK
  • Page 219 – RCHBLK is programmed to block channel 1.
  • Page 222 – RECEIVE IBO CHANNEL INTERLEAVE MODE TIMING
  • Page 223 – RECEIVE IBO FRAME INTERLEAVE MODE TIMING
  • Page 225 – TRANSMIT SIDE TIMING; TLINK is programmed to source just the Sa4 bit.; TSSYNC
  • Page 226 – TRANSMIT SIDE BOUNDARY TIMING
  • Page 227 – TSYSCLK
  • Page 229 – TRANSMIT IBO CHANNEL INTERLEAVE MODE TIMING; TSYNC is in input mode
  • Page 230 – TRANSMIT IBO FRAME INTERLEAVE MODE TIMING
  • Page 231 – OPERATING PARAMETERS
  • Page 232 – RECOMMENDED DC OPERATING CONDITIONS
  • Page 233 – AC TIMING PARAMETERS AND DIAGRAMS
  • Page 236 – Nonmultiplexed Bus AC Characteristics
  • Page 237 – Address Valid
  • Page 239 – Receive Side AC Characteristics
  • Page 242 – RECEIVE LINE INTERFACE TIMING
  • Page 243 – Transmit AC Characteristics
  • Page 245 – TRANSMIT SIDE TIMING, EL ASTIC STORE ENABLED
  • Page 246 – TRANSMIT LINE INTERFACE TIMING
  • Page 247 – MECHANICAL DESCRIPTIONS
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Product Preview

DS21Q55

Note :

This Product Preview contains preliminary information and is subject to change without notice.

Some revisions of this device may incorporate deviations from published specifications known as errata.
Multiple revisions of any device may be simultaneously available through various sales channels. For
information about device errata, visit:

http://dbserv.maxim -ic.com/errata.cfm

.

Please contact

[email protected]

or search

http://www.maxim -ic.com

for updated

information.

X




FEATURES:

Complete T1 (DS1)/ISDN–PRI/J1 transceiver
functionality

§

Complete E1 (CEPT) PCM-30/ISDN -PRI
transceiver functionality

§

Short- and long-haul line interface for
clock/data recovery and wave shaping

§

CMI coder/decoder

§

Crystal- less jitter attenuator

§

Dual HDLC controllers

§

On-chip programmable BERT generator and
detector

§

Internal software-selectable receive and
transmit side termination resistors

§

Dual two- frame elastic-store slip buffers to
interface backplanes up to 16.384MHz

§

16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz clock output synthesized to
recovered network clock

§

Programmable output clocks for fractional
T1, E1, H0, and H12 applications

§

Interleaving PCM bus operation

§

8-bit parallel control port, multiplexed or
nonmultiplexed, Intel or Motorola

§

IEEE 1149.1 JTAG-boundary scan

§

3.3V supply with 5V tolerant I/O

§

Signaling System 7 (SS7) support

APPLICATIONS:

§

Routers

§

Channel Service Units (CSUs)

§

Data Service Units (DSUs)

§

Muxes

§

Switches

§

Channel Banks

§

T1/E1 Test Equipment

§

DSL Add/Drop Multiplexers

ORDERING INFORMATION

DS21Q55

27mm BGA (0

°

C to +70

°

C)

DS21Q55N 27mm BGA (-40

°

C to +85

°

C)














1. DESCRIPTION

The DS21Q55 is a quad MCM device featuring independent transceivers that can be software configured
for T1, E1, or J1 operation. Each is composed of a line interface unit (LIU), framer, HDLC controllers,
and a TDM backplane interface, and is controlled via an 8-bit parallel port configured for Intel or
Motorola bus operations. The DS21Q55 is software compatible with the DS2155 single transceiver. It is
pin compatible with the DS21Qx5y family of products.

PRODUCT PREVIEW

DS21Q55 Quad T1/E1/J1 Transceiver

www.maxim-ic.com

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Summary

Page 2 - Please contact

Product Preview DS21Q55 2 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 1. DESCRIPTION The DS21Q55 is a quad MCM devices featuring independent transceivers that can be software configured for T1, E1, or J1 operation. Each is comp...

Page 4 - FEATURE HIGHLIGHTS

Product Preview DS21Q55 4 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 1.1 FEATURE HIGHLIGHTS The DS21Q55 contains all of the features of the previous generation of Dallas Semiconductor’s T1 and E1 transceivers plus many new fea...

Page 8 - TABLE OF CONTENTS

Product Preview DS21Q55 8 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. TABLE OF CONTENTS 1.1 FEATURE HIGHLIGHTS .......................................................................................................................

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