Maxim DS21Q55 - Manuals - manualsarea.com

Page 2 - Please contact

Product Preview DS21Q55 2 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 1. DESCRIPTION The DS21Q55 is a quad MCM devices featuring independent transceivers that can be software configured for T1, E1, or J1 operation. Each is comp...

Page 4 - FEATURE HIGHLIGHTS

Product Preview DS21Q55 4 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 1.1 FEATURE HIGHLIGHTS The DS21Q55 contains all of the features of the previous generation of Dallas Semiconductor’s T1 and E1 transceivers plus many new fea...

Page 8 - TABLE OF CONTENTS

Product Preview DS21Q55 8 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. TABLE OF CONTENTS 1.1 FEATURE HIGHLIGHTS .......................................................................................................................

Page 11 - OPERATING PARAMETERS; MECHANICAL DESCRIPTIONS

Product Preview DS21Q55 11 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 32.2 E1 M ODE .................................................................................................................................................

Page 12 - DOCUMENT REVISION HISTORY; Initial Preliminary Release

Product Preview DS21Q55 12 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 1.2 DOCUMENT REVISION HISTORY 1) Initial Preliminary Release

Page 13 - BLOCK DIAGRAM

Product Preview DS21Q55 13 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 2. BLOCK DIAGRAM A simplified block diagram showing the major components of the DS21Q55 is shown in Figure 4-1. Details are shown in subsequent figures. The...

Page 14 - PIN FUNCTION DESCRIPTION

Product Preview DS21Q55 14 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 3. PIN FUNCTION DESCRIPTION 3.1 Transmit Side Pins Signal Name: TCLKx Signal Description: Transmit Clock Signal Type: Input A 1.544 MHz or a 2.048MHz primar...

Page 18 - Parallel Control Port Pins

Product Preview DS21Q55 18 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Signal Name: BPCLKx Signal Description: Back Plane Clock Signal Type: Outpu t A u s e r-selectable synthesized clock output that is referenced to the clock ...

Page 20 - JTAG Test Access Port Pins

Product Preview DS21Q55 20 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Signal Name: A7/ALE(AS ) Signal Description: A7 or Address Latch Enable(Address Strobe) Signal Type: Input In nonmultiplexed bus operation (MUX = 0), it ser...

Page 21 - Line Interface Pins

Product Preview DS21Q55 21 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Signal Name: JTCLK Signal Description: IEEE 1149.1 Test Clock Signal Signal Type: Input This signal is used to shift data into JTDI on the rising edge and o...

Page 23 - PIN

Product Preview DS21Q55 23 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 3.8 Pinout DS21Q55 PIN DESCRIPTION Table 5-1 NOTE: Signal is common to all transceivers unless otherwise stated PIN SYMBOL TYPE DESCRIPTION U3 A0 I Address ...

Page 30 - Register Map; REGISTER MAP SORTED BY ADDRESS; ADDRESS

Product Preview DS21Q55 30 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 4. PARALLEL PORT The DS21Q55 is controlled via a nonmultiplexed (MUX = 0) or a multiplexed (MUX = 1) bus by an external microcontroller or microprocessor. T...

Page 36 - SPECIAL PER-CHANNEL REGISTER OPERATION; PCPR

Product Preview DS21Q55 36 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 5. SPECIAL PER-CHANNEL REGISTER OPERATION Some of the features described in the data sheet that operate on a per-channel basis use a special method for chan...

Page 37 - PCDR1

Product Preview DS21Q55 37 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: PCDR1 Register Description: Per-Channel Data Register 1 Register Address: 29h Bit # 7 6 5 4 3 2 1 0 Name Default CH8 CH7 CH6 CH5 CH4 CH3 CH2 ...

Page 38 - PROGRAMMING MODEL; Issue Reset

Product Preview DS21Q55 38 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 6. PROGRAMMING MODEL The DS21Q55 register map is divided into three groups: T1 specific features, E1 specific features, and common features. The typical pro...

Page 39 - MSTRREG

Product Preview DS21Q55 39 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 6.1 Power-Up Sequence The DS21Q55 contains an on-chip power-up reset function, which automatically clears the writeable register space immediately after pow...

Page 40 - Interrupt Handling; ESIB; Status Registers

Product Preview DS21Q55 40 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 6.2 Interrupt Handling Various alarms, conditions, and events in the DS21Q55 can cause interrupts. For simplicity, these are all referred to as events in th...

Page 41 - Information Registers; Interrupt Information Register 1

Product Preview DS21Q55 41 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. marked as “double interrupt bits.” An interrupt will be produced when the condition occurs and when it clears. 6.4 Information Registers Information registe...

Page 42 - CLOCK MAP; TRANSMIT CLOCK SOURCE

Product Preview DS21Q55 42 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 7. CLOCK MAP Figure 9-1 shows the clock map of the DS21Q55. The routing for the transmit and receive clocks are shown for the various loopback modes and jit...

Page 43 - T1 FRAMER/FORMATTER CONTROL REGISTERS; T1 Receive Control Register 1

Product Preview DS21Q55 43 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 8. T1 FRAMER/FORMATTER CONTROL REGISTERS The T1 framer portion of the DS21Q55 is configured via a set of nine control registers. Typically, the control regi...

Page 44 - T1 Receive Control Register 2

Product Preview DS21Q55 44 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: T1RCR2 Register Description: T1 Receive Control Register 2 Register Address: 0 4 h Bit # 7 6 5 4 3 2 1 0 Name - RFM RB8ZS RSLC96 RZSE RZBTSI ...

Page 45 - T1 Transmit Control Register 1

Product Preview DS21Q55 45 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: T1TCR1 Register Description: T1 Transmit Control Register 1 Register Address: 0 5 h Bit # 7 6 5 4 3 2 1 0 Name TJC TFPT TCPT TSSE GB7S TFDLS ...

Page 46 - T1 Transmit Control Register 2

Product Preview DS21Q55 46 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: T1TCR2 Register Description: T1 Transmit Control Register 2 Register Address: 0 6 h Bit # 7 6 5 4 3 2 1 0 Name TB8ZS TSLC96 TZSE FBCT2 FBCT1 ...

Page 47 - T1 Common Control Register 1

Product Preview DS21Q55 47 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: T1CCR1 Register Description: T1 Common Control Register 1 Register Address: 0 7 h Bit # 7 6 5 4 3 2 1 0 Name - - - - - TFM PDE TLOOP Default ...

Page 48 - T1 Transmit Transparency

Product Preview DS21Q55 48 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 8.2 T1 Transmit Transparency The software-signaling insertion-enable registers, SSIE1 –SSIE4, can be used to select signaling insertion from the transmit-si...

Page 49 - T1 Receive Digital Milliwatt Enable Register 1

Product Preview DS21Q55 49 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: T1RDMR1 Register Descriptio n: T1 Receive Digital Milliwatt Enable Register 1 Register Address: 0Ch Bit # 7 6 5 4 3 2 1 0 Name CH8 CH7 CH6 CH...

Page 50 - T1 Information Register; Information Register 1

Product Preview DS21Q55 50 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 8.4 T1 Information Register Register Name: INFO1 Register Description: Information Register 1 Register Address: 1 0 h Bit # 7 6 5 4 3 2 1 0 Name RPDV TPDV C...

Page 51 - T1 ALARM CRITERIA; ALARM; Blue Alarm

Product Preview DS21Q55 51 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. T1 ALARM CRITERIA Table 10-1 ALARM SET CRITERIA CLEAR CRITERIA Blue Alarm (AIS) (Note 1) Over a 3ms window, five or fewer zeros are received Over a 3ms wind...

Page 52 - E1 FRAMER/FORMATTER CONTROL REGISTERS; E1 Receive Control Register 1

Product Preview DS21Q55 52 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 9. E1 FRAMER/FORMATTER CONTROL REGISTERS The E1 framer portion of the DS21Q55 is configured via a set of four control registers. Typically, the control regi...

Page 53 - E1 SYNC/RESYNC CRITERIA; FRAME OR; FAS; E1 Receive Control Register 2

Product Preview DS21Q55 53 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. E1 SYNC/RESYNC CRITERIA Table 11 -1 FRAME OR MULTIFRAME LEVEL SYNC CRITERIA RESYNC CRITERIA ITU SPEC. FAS FAS present in frame N and N + 2, and FAS not pres...

Page 54 - E1 Transmit Control Register 1

Product Preview DS21Q55 54 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: E1TCR1 Register Description: E1 Transmit Control Register 1 Register Address: 3 5 h Bit # 7 6 5 4 3 2 1 0 Name TFPT T16S TUA1 TSiS TSA1 THDB3...

Page 55 - E1 Transmit Control Register 2

Product Preview DS21Q55 55 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: E1TCR2 Register Description: E1 Transmit Control Register 2 Register Address: 3 6 h Bit # 7 6 5 4 3 2 1 0 Name Sa8S Sa7S Sa6S Sa5S Sa4S A EBE...

Page 56 - Automatic Alarm Generation; enabled at the same time.

Product Preview DS21Q55 56 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 9.2 Automatic Alarm Generation The device can be programmed to automatically transmit AIS or remote alarm. When automat ic AIS generation is enabled (E1TCR2...

Page 57 - E1 Information Registers; Information Register 3

Product Preview DS21Q55 57 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 9.3 E1 Information Registers Register Name: INFO3 Register Description: Information Register 3 Register Address: 1 2 h Bit # 7 6 5 4 3 2 1 0 Name - - - - - ...

Page 58 - E1 ALARM CRITERIA; An

Product Preview DS21Q55 58 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. E1 ALARM CRITERIA Table 11-2 ALARM SET CRITERIA CLEAR CRITERIA ITU SPEC. RLOS An RLOS condition exists on power- up prior to initial synchronization, when a...

Page 59 - COMMON CONTROL AND STATUS REGISTERS; Common Control Register 1

Product Preview DS21Q55 59 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 10. COMMON CONTROL AND STATUS REGISTERS Register Name: CCR1 Register Description: Common Control Register 1 Register Address: 7 0 h Bit # 7 6 5 4 3 2 1 0 Na...

Page 60 - IDR

Product Preview DS21Q55 60 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: IDR Register Description: Device Identification Register Register Address: 0Fh Bit # 7 6 5 4 3 2 1 0 Name ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 Def...

Page 61 - Interrupt Mask Re gister 2

Product Preview DS21Q55 61 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: IMR2 Register Description: Interrupt Mask Re gister 2 Register Address: 1 9 h Bit # 7 6 5 4 3 2 1 0 Name RYELC RUA1C FRCLC RLOSC RYEL RUA1 FR...

Page 62 - Status Register 3

Product Preview DS21Q55 62 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: SR3 Register Description: Status Register 3 Register Address: 1Ah Bit # 7 6 5 4 3 2 1 0 Name LSPARE LDN LUP LOTC LORC V52LNK RDMA RRA Default...

Page 63 - Interrupt Mask Register 3

Product Preview DS21Q55 63 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: IMR3 Register Description: Interrupt Mask Register 3 Register Address: 1Bh Bit # 7 6 5 4 3 2 1 0 Name LSPARE LDN LUP LOTC LORC V52LNK RDMA RR...

Page 64 - Status Register 4

Product Preview DS21Q55 64 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: SR4 Register Description: Status Register 4 Register Address: 1Ch Bit # 7 6 5 4 3 2 1 0 Name - RSA1 RSA0 TMF TAF RMF RCMF RAF Default 0 0 0 0...

Page 65 - Interrupt Mask Register 4

Product Preview DS21Q55 65 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: IMR4 Register Description: Interrupt Mask Register 4 Register Address: 1Dh Bit # 7 6 5 4 3 2 1 0 Name - RSA1 RSA0 TMF TAF RMF RCMF RAF Defaul...

Page 66 - I/O Configuration Register 1

Product Preview DS21Q55 66 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 11. I/O PIN CONFIGURATION OPTIONS Register Name: IOCR1 Register Description: I/O Configuration Register 1 Register Address: 0 1 h Bit # 7 6 5 4 3 2 1 0 Name...

Page 67 - I/O Configuration Register 2

Product Preview DS21Q55 67 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: IOCR2 Register Description: I/O Configuration Register 2 Register Address: 0 2 h Bit # 7 6 5 4 3 2 1 0 Name RCLKINV TCLKINV RSYNCINV TSYNCINV...

Page 68 - LOOPBACK CONFIGURATION; LBCR

Product Preview DS21Q55 68 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 12. LOOPBACK CONFIGURATION Register Name: LBCR Register Description: Loopback Control Register Register Address: 4Ah Bit # 7 6 5 4 3 2 1 0 Name - - - LIUC L...

Page 70 - Per-Channel Loopback Enable Register 1

Product Preview DS21Q55 70 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 12.1 Per-Channel Loopback The per-channel loopback registers (PCLRs) determine which channels (if any) from the backplane should be replaced with the data f...

Page 71 - Per-Channel Loopback Enable Register 3

Product Preview DS21Q55 71 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: PCLR3 Register Description: Per-Channel Loopback Enable Register 3 Register Address: 4Dh Bit # 7 6 5 4 3 2 1 0 Name CH24 CH23 CH22 CH21 CH20 ...

Page 72 - ERROR COUNT REGISTERS; Note; ERCNT

Product Preview DS21Q55 72 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 13. ERROR COUNT REGISTERS The DS21Q55 contains four counters that are used to accumulate line coding errors, path errors, and synchronization errors. Counte...

Page 73 - T1 Operation; T1 LINE CODE VIOLATION COUNTING OPTIONS; COUNT EXCESSIVE; E1 LINE CODE VIOLATION COUNTING OPTIONS; E1 CODE VIOLATION SELECT

Product Preview DS21Q55 73 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 13.1 Line Code Violation Count Register (LCVCR) T1 Operation T1 code violations are defined as bipolar violations (BPVs) or excessive zeros. If the B8ZS mod...

Page 74 - Line Code Violation Count Register 1

Product Preview DS21Q55 74 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: LCVCR1 Register Description: Line Code Violation Count Register 1 Register Address: 4 2 h Bit # 7 6 5 4 3 2 1 0 Name LCVC15 LCVC14 LCVC13 LCV...

Page 75 - T1 PATH CODE VIOLATION COUNTING ARRANGEMENTS; FRAMING MODE

Product Preview DS21Q55 75 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 13.2 Path Code Violation Count Register (PCVCR) T1 Operation The path-code violation-count register records either Ft, Fs, or CRC6 errors in T1 frames. When...

Page 76 - Path Code Violation Count Register 1; T1 FRAMES OUT OF SYNC COUNTING ARRANGEMENTS

Product Preview DS21Q55 76 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: PCVCR1 Register Description: Path Code Violation Count Register 1 Register Address: 4 4 h Bit # 7 6 5 4 3 2 1 0 Name PCVC15 PCVC14 PCVC13 PCV...

Page 78 - Frames Out Of Sync Count Register 1

Product Preview DS21Q55 78 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: FOSCR1 Register Description: Frames Out Of Sync Count Register 1 Register Address: 4 6 h Bit # 7 6 5 4 3 2 1 0 Name FOS15 FOS14 FOS13 FOS12 F...

Page 79 - DS0 MONITORING FUNCTION; TDS0SEL

Product Preview DS21Q55 79 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 14. DS0 MONITORING FUNCTION The DS21Q55 has the ability to monitor one DS0 64kbps channel in the transmit direction and one DS0 channel in the receive direc...

Page 80 - Receive DS0 Monitor Registers; RDS0SEL

Product Preview DS21Q55 80 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 14.2 Receive DS0 Monitor Registers Register Name: RDS0SEL Register Description: Receive Channel Monitor Select Register Address: 7 6 h Bit # 7 6 5 4 3 2 1 0...

Page 81 - SIGNALING OPERATION

Product Preview DS21Q55 81 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 15. SIGNALING OPERATION There are two methods to access receive signaling data and provide transmit signaling data: processor-based (i.e., software-based) o...

Page 83 - SIGCR; must be set to zero for proper operation.

Product Preview DS21Q55 83 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. registers for T1 mode and PCDR1 -PCDR4 registers for E1 mode. In E1 mode, the user will generally select all channels when doing reinsertion. 15.1.2.2 Force...

Page 85 - Receive Signaling Registers

Product Preview DS21Q55 85 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: RS1 to RS16 Register Description: Receive Signaling Registers (E1 Mode, CAS Format) Register Address: 60h to 6Fh (MSB) (LSB) 0 0 0 0 X Y X X ...

Page 87 - Transmit Signaling

Product Preview DS21Q55 87 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 15.2 Transmit Signaling SIMPLIFIED DIAGRAM OF TRANSMIT SIGNALING PATH Figure 17-2 15.2.1 Processor-Based Transmit Signaling In processor-based mode, signali...

Page 88 - TIME SLOT NUMBERING SCHEMES; TS

Product Preview DS21Q55 88 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 15.2.1.1 T1 Mode In T1 ESF framing mode, there are four signaling bits per channel (A, B, C, and D). TS1– TS12 contain a full multiframe of signaling data. ...

Page 89 - Transmit Signaling Registers

Product Preview DS21Q55 89 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: TS1 to TS16 Register Description: Transmit Signaling Registers (E1 Mode, CAS Format) Register Address: 50h to 5Fh (MSB) (LSB) 0 0 0 0 X Y X X...

Page 93 - Software Signaling Insertion Enable Registers, E1 CAS Mode; Software Signaling Insertion Enable 1

Product Preview DS21Q55 93 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 15.2.2 Software Signaling Insertion Enable Registers, E1 CAS Mode In E1 CAS mode, the CAS signaling alignment/alarm byte can be sourced from the transmit si...

Page 94 - SSIE3

Product Preview DS21Q55 94 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: SSIE3 Register Description: Software Signaling Insertion Enable 3 Register Address: 0Ah Bit # 7 6 5 4 3 2 1 0 Name CH22 CH21 CH20 CH19 CH18 C...

Page 95 - Software Signaling Insertion Enable Registers, T1 Mode

Product Preview DS21Q55 95 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 15.2.3 Software Signaling Insertion Enable Registers, T1 Mode In T1 mode, only registers SSIE1 through SSIE3 are used since t here are only 24 channels in a...

Page 97 - IDLE CODE ARRAY ADDRESS MAPPING; BITS 0–5 OF IAAR REGISTER

Product Preview DS21Q55 97 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 16. PER-CHANNEL IDLE CODE GENERATION Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions. When operat...

Page 98 - Idle Code Programming Examples; The following example sets all transmit idle codes to 7Eh:

Product Preview DS21Q55 98 of 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 16.1 Idle Code Programming Examples The following e xample sets transmit channel 3 idle code to 7Eh: Write IAAR = 02h ;select channel 3 in the array Write P...

Page 101 - Transmit Channel Idle Code Enable Register

Product Preview DS21Q55 101 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: TCICE3 Register Description: Transmit Channel Idle Code Enable Register 3 Register Address: 8 2 h Bit # 7 6 5 4 3 2 1 0 Name CH24 CH23 CH22...

Page 102 - Receive Ch annel Idle Code Enable Register 3

Product Preview DS21Q55 102 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: RCICE3 Register Description: Receive Ch annel Idle Code Enable Register 3 Register Address: 8 6 h Bit # 7 6 5 4 3 2 1 0 Name CH24 CH23 CH22...

Page 103 - CHANNEL BLOCKING REGISTERS; Fractional T1/E1 Support; Receive Channel Blocking Register 1

Product Preview DS21Q55 103 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 17. CHANNEL BLOCKING REGISTERS The receive-channel blocking registers (RCBR1 /RCBR2 /RCBR3 /RCBR4 ) and the transmit-channel blocking registers (TCBR1 /TC...

Page 104 - Receive Channel Blocking Register 3

Product Preview DS21Q55 104 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: RCBR3 Register Description: Receive Channel Blocking Register 3 Register Address: 8Ah Bit # 7 6 5 4 3 2 1 0 Name CH24 CH23 CH22 CH21 CH20 C...

Page 105 - Transmit Channel Blocking Register 3

Product Preview DS21Q55 105 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: TCBR3 Register Description: Transmit Channel Blocking Register 3 Register Address: 8Eh Bit # 7 6 5 4 3 2 1 0 Name CH24 CH23 CH22 CH21 CH20 ...

Page 106 - ELASTIC STORES OPERATION; Interleaved PCM Bus Operation.

Product Preview DS21Q55 106 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 18. ELASTIC STORES OPERATION The DS21Q55 contains dual two- frame, fully independent elastic stores, one for the receive direction and one for the transmi...

Page 107 - ESCR

Product Preview DS21Q55 107 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: ESCR Register Description: Elastic Store Control Register Register Address: 4Fh Bit # 7 6 5 4 3 2 1 0 Name TESALGN TESR TESMDM TESE RESALGN...

Page 108 - Status Register 5

Product Preview DS21Q55 108 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: SR5 Register Description: Status Register 5 Register Address: 1Eh Bit # 7 6 5 4 3 2 1 0 Name - - TESF TESEM TSLIP RESF RESEM RSLIP Default ...

Page 111 - Elastic Stores Initialization; INITIALIZATION

Product Preview DS21Q55 111 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 18.2 Transmit Side See the IOCR1 and IOCR2 registers for information on clock and I/O configurations. The operation of the transmit elastic store is very ...

Page 113 - CRC-4 RECALCULATE METHOD

Product Preview DS21Q55 113 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 19. G.706 INT ERMEDIATE CRC-4 UPDATING (E1 MODE ONLY) The DS21Q55 can implement the G.706 CRC -4 recalculation at intermediate path points. When this mode...

Page 115 - BOCC

Product Preview DS21Q55 115 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: BOCC Register Description: BOC Control Register Register Address: 3 7 h Bit # 7 6 5 4 3 2 1 0 Name - - - RBOCE RBR RBF1 RBF0 SBOC Default 0...

Page 116 - RFDL

Product Preview DS21Q55 116 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: RFDL (RFDL register bit usage when BOCC.4 = 1) Register Description: Receive FDL Register Register Address: C0h Bit # 7 6 5 4 3 2 1 0 Name ...

Page 117 - Interrupt Mask Register 8

Product Preview DS21Q55 117 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: IMR8 Register Description: Interrupt Mask Register 8 Register Address: 2 5 h Bit # 7 6 5 4 3 2 1 0 Name - - BOCC RFDLAD RFDLF TFDLE RMTCH R...

Page 119 - RAF

Product Preview DS21Q55 119 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: RAF Register Description: Receive Align Frame Register Register Address: C6h Bit # 7 6 5 4 3 2 1 0 Name Si 0 0 1 1 0 1 1 Default 0 0 0 0 0 ...

Page 120 - T A F

Product Preview DS21Q55 120 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: T A F Register Description: Transmit Align Frame Register Register Address: D0h Bit # 7 6 5 4 3 2 1 0 Name Si 0 0 1 1 0 1 1 Default 0 0 0 1...

Page 121 - Internal Register Scheme Based On CRC4 Multiframe (Method 3); RSiAF; Receive Si Bits of the Al ign Frame

Product Preview DS21Q55 121 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 21.3 Internal Register Scheme Based On CRC4 Multiframe (Method 3) On the receive side, the re is a set of eight registers (RSiAF , RSiNAF, RRA, RSa4 to RS...

Page 122 - RSiNAF

Product Preview DS21Q55 122 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: RSiNAF Register Description: Receive Si Bits of the Nonalign Frame Register Address: C9h Bit # 7 6 5 4 3 2 1 0 Name SiF1 SiF3 SiF5 SiF7 SiF...

Page 123 - Receive Sa4 Bits

Product Preview DS21Q55 123 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: RSa4 Register Description: Receive Sa4 Bits Register Address: CBh Bit # 7 6 5 4 3 2 1 0 Name RSa4F1 RSa4F3 RSa4F5 RSa4F7 RSa4F9 RSa4F11 RSa...

Page 124 - Receive Sa6 Bits

Product Preview DS21Q55 124 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: RSa6 Register Description: Receive Sa6 Bits Register Address: CDh Bit # 7 6 5 4 3 2 1 0 Na me RSa6F1 RSa6F3 RSa6F5 RSa6F7 RSa6F9 RSa6F11 RS...

Page 125 - Receive Sa8 Bits

Product Preview DS21Q55 125 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: RSa8 Register Description: Receive Sa8 Bits Register Address: CFh Bit # 7 6 5 4 3 2 1 0 Name RSa8F1 RSa8F3 RSa8F5 RSa8F7 RSa8F9 RSa8F11 RSa...

Page 126 - TSiAF; Transmit Si Bits of the Align Frame

Product Preview DS21Q55 126 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: TSiAF Register Description: Transmit Si Bits of the Align Frame Register Address: D2h Bit # 7 6 5 4 3 2 1 0 Name TsiF0 TsiF2 TsiF4 TsiF6 Ts...

Page 127 - TSiNAF

Product Preview DS21Q55 127 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: TSiNAF Register Description: Transmit Si Bits of the Nonalign Frame Register Address: D3h Bit # 7 6 5 4 3 2 1 0 Name TsiF1 TsiF3 TsiF5 TsiF...

Page 128 - Transmit Sa4 Bits

Product Preview DS21Q55 128 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: TSa4 Register Description: Transmit Sa4 Bits Register Address: D5h Bit # 7 6 5 4 3 2 1 0 Name TSa4F1 TSa4F3 TSa4F5 TSa4F7 TSa4F9 TSa4F11 TS...

Page 129 - Transmit Sa6 Bits

Product Preview DS21Q55 129 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: TSa6 Register Description: Transmit Sa6 Bits Register Address: D7h Bit # 7 6 5 4 3 2 1 0 Name TSa6F1 TSa6F3 TSa6F5 TSa6F7 TSa6F9 TSa6F11 TS...

Page 130 - Transmit Sa8 Bits

Product Preview DS21Q55 130 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: TSa8 Register Description: Transmit Sa8 Bits Register Address: D9h Bit # 7 6 5 4 3 2 1 0 Name TSa8F1 TSa8F3 TSa8F5 TSa8F7 TSa8F9 TSa8F11 TS...

Page 131 - TSACR

Product Preview DS21Q55 131 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: TSACR Register Description: Transmit Sa Bit Control Register Register Address: DAh Bit # 7 6 5 4 3 2 1 0 Name SiAF SiNAF RA Sa4 Sa5 Sa6 Sa7...

Page 132 - HDLC CONTROLLERS

Product Preview DS21Q55 132 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 22. HDLC CONTROLLERS This device has two enhanced HDLC controllers, HDLC #1 and HDLC #2. Each controller is configurable for use with time slots, or Sa4 t...

Page 133 - HDLC CONTROLLER REGISTERS; NAME

Product Preview DS21Q55 133 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. HDLC CONTROLLER REGISTERS Table 24-1 NAME FUNCTION CONTROL/CONFIGURATION H1TC , HDLC #1 Transmit Control Register H2TC , HDLC #2 Transmit Control Register...

Page 134 - HDLC Configuration

Product Preview DS21Q55 134 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 22.2 HDLC Configuration Basic configuration of the HDLC controllers is accomplished via the HxTC and HxRC registers. Operating features such as CRC genera...

Page 137 - REGISTER; HxRCS1

Product Preview DS21Q55 137 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 22.3 HDLC Mapping 22.3.1 Receive The HDLC controllers need to be assigned a space in the T1/E1 bandwidth in which they will transmit and receive data. The...

Page 139 - HxTCS1

Product Preview DS21Q55 139 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 22.3.2 Transmit The HxTCS1–HxTCS4 registers are used to assign the transmit controllers to channels 1–24 (T1) or 1–32 (E1), according to the following tab...

Page 143 - PACKET STATUS

Product Preview DS21Q55 143 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: INFO5 , INFO6 Register Description: HDLC #1 Information Register HDLC #2 Information Register Register Address: 2Eh, 2Fh Bit # 7 6 5 4 3 2 ...

Page 144 - Bits 0 to 7/Transmit FIFO Bytes Available; Receive Packet Bytes Available

Product Preview DS21Q55 144 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 22.3.3 FIFO Information The transmit FIFO buffer-available register indicates the number of bytes that can be written into the transmit FIFO. The count fr...

Page 146 - Receive HDLC Code Example

Product Preview DS21Q55 146 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 22.4 Receive HDLC Code Example Below is an example of a receive HDLC routine for controller #1. 1) Reset receive HDLC controller 2) Set HDLC mode, mapping...

Page 148 - TFDL

Product Preview DS21Q55 148 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 22.5.2 Transmit Section The transmit section will shift out into the T1 data stream, either the FDL (in the ESF framing mode) or the Fs bits (in the D4 fr...

Page 149 - BASIC NETWORK CONNECTIONS

Product Preview DS21Q55 149 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 23. LINE INTERFACE UNIT (LIU) The LIU in the DS21Q55 contains three sections: the receiver, which handles clock and data recovery; the transmitter, whic h...

Page 151 - Receive Level Indicator and Threshold Interrupt

Product Preview DS21Q55 151 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 23.2.1 Receive Level Indicator and Threshold Interrupt The DS21Q55 reports the signal strength at RTIP and RRING in 2.5dB increments through RL3 –RL0 loca...

Page 152 - LIU Transmitter; register

Product Preview DS21Q55 152 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 23.3 LIU Transmitter The DS21Q55 uses a phase- lock loop along with a precision digital-to-analog converter (DAC) to create the waveforms that are transmi...

Page 153 - MCLK Prescaler; CLOCK

Product Preview DS21Q55 153 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 23.4 MCLK Prescaler A 16.384MHz, 8.192MHz, 4.096MHz, 2.048MHz, or 1.544MHz clock must be applied at MCLK. ITU specification G.703 requires an accuracy of ...

Page 154 - LIU Control Registers; Line Interface Control 1

Product Preview DS21Q55 154 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 23.7 LIU Control Registers Register Name: LIC1 Register Description: Line Interface Control 1 Register Address: 7 8 h Bit # 7 6 5 4 3 2 1 0 Name L2 L1 L0 ...

Page 155 - E1 Mode; APPLICATION

Product Preview DS21Q55 155 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. E1 Mode L2 L1 L0 APPLICATION N ( 1 ) RETURN LOSS Rt (1) 0 0 0 75O normal 1:2 NM 0 0 0 1 120O normal 1:2 NM 0 1 0 0 75O with high return loss* 1:2 21dB 6.2...

Page 157 - Line Interface Control 2

Product Preview DS21Q55 157 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: LIC2 Register Description: Line Interface Control 2 Register Address: 7 9 h Bit # 7 6 5 4 3 2 1 0 Name ETS LIRST IBPV TUA1 JAMUX - SCLD CLD...

Page 158 - Line Interface Control 3

Product Preview DS21Q55 158 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: LIC3 Register Description: Line Interface Control 3 Register Address: 7Ah Bit # 7 6 5 4 3 2 1 0 Name - TCES RCES MM1 MM0 RSCLKE TSCLKE TAOZ...

Page 160 - Information Register 2

Product Preview DS21Q55 160 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: INFO2 Register Description: Information Register 2 Register Address: 1 1 h Bit # 7 6 5 4 3 2 1 0 Name BSYNC - TCLE TOCD RL3 RL2 RL1 RL0 Def...

Page 161 - Common Control Register 4

Product Preview DS21Q55 161 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: CCR4 Register Description: Common Control Register 4 Register Address: 73h Bit # 7 6 5 4 3 2 1 0 Name RLT3 RLT2 RLT1 RLT0 — — — — Default 0...

Page 162 - Status Register 1

Product Preview DS21Q55 162 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: SR1 Register Description: Status Register 1 Register Address: 1 6 h Bit # 7 6 5 4 3 2 1 0 Name ILUT TIMER RSCOS JALT LRCL TCLE TOCD LOLITC ...

Page 163 - Interrupt Mask Register 1

Product Preview DS21Q55 163 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: IMR1 Register Description: Interrupt Mask Register 1 Register Address: 1 7 h Bit # 7 6 5 4 3 2 1 0 Name - TIMER RSCOS JALT LRCL TCLE TOCD L...

Page 164 - Recommended Circuits

Product Preview DS21Q55 164 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 23.8 Recommended Circuits BASIC INTERFACE Figure 25-4 NOTES: 1) All resistor values are ±1%. 2) Resistors R should be set to 60O each if the internal rece...

Page 165 - PROTECTED INTERFACE USING INTERNAL RECEIVE TERMINATION; X1 and X2 are very low DCR transformers

Product Preview DS21Q55 165 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. PROTECTED INTERFACE USING INTERNAL RECEIVE TERMINATION Figure 25-5 NOTES: 1) All resistor values are ±1%. 2) X1 and X2 are very low DCR transformers 3) C1...

Page 166 - Component Specifications; SPECIFICATION

Product Preview DS21Q55 166 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 23.9 Component Specifications TRANSFORMER SPECIFICATIONS Table 25-1 SPECIFICATION RECOMMENDED VALUE Turns Ratio 3.3V Applications 1:1 (receive) and 1:2 (t...

Page 167 - E1 TRANSMIT PULSE TEMPLATE

Product Preview DS21Q55 167 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. E1 TRANSMIT PULSE TEMPLATE Figure 25-6 T1 TRANSMIT PULSE TEMPLATE Figure 25-7 0 -0.1 -0.2 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 0 TIME (ns) SCAL...

Page 169 - E1 MODE

Product Preview DS21Q55 169 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. JITTER ATTENUATION (T1 MODE) Figure 25-10 JITTER ATTENUATION (E1 MODE) Figure 25-11 FREQUENCY (Hz) 0dB -20dB -40dB -60dB 1 1 0 100 1K 10K JITTER ATTENUATI...

Page 170 - PROGRAMMABLE IN- BAND LOOP CODE GENERATION AND DETECTION; This function is available only in T1 mode; . To transmit a pattern, the user will load the pattern

Product Preview DS21Q55 170 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 24. PROGRAMMABLE IN- BAND LOOP CODE GENERATION AND DETECTION The DS21Q55 has the ability to generate and detect a repeating bit pattern from 1 bit to 8 bi...

Page 171 - IBCC; In-Band Code Control Register

Product Preview DS21Q55 171 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: IBCC Register Description: In-Band Code Control Register Register Address: B6h Bit # 7 6 5 4 3 2 1 0 Name TC1 TC0 RUP2 RUP1 RUP0 RDN2 RDN1 ...

Page 172 - Transmit Code Definition Register 1

Product Preview DS21Q55 172 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: TCD1 Register Description: Transmit Code Definition Register 1 Register Address: B7h Bit # 7 6 5 4 3 2 1 0 Name C7 C6 C5 C4 C3 C2 C1 C0 Def...

Page 173 - Receive - Up Code Definition Register 1

Product Preview DS21Q55 173 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: RUPCD1 Register Description: Receive - Up Code Definition Register 1 Register Address: B9h Bit # 7 6 5 4 3 2 1 0 Name C7 C6 C5 C4 C3 C2 C1 ...

Page 174 - Receive - Down Code Definition Register 1

Product Preview DS21Q55 174 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: RDNCD1 Register Description: Receive - Down Code Definition Register 1 Register Address: BBh Bit # 7 6 5 4 3 2 1 0 Name C7 C6 C5 C4 C3 C2 C...

Page 175 - Receive - Down Code Definition Register 2

Product Preview DS21Q55 175 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: RDNCD2 Register Description: Receive - Down Code Definition Register 2 Register Address: BCh Bit # 7 6 5 4 3 2 1 0 Name C7 C6 C5 C4 C3 C2 C...

Page 176 - Receive -Spare Code Definition Register 1

Product Preview DS21Q55 176 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: RSCD1 Register Description: Receive -Spare Code Definition Register 1 Register Address: BEh Bit # 7 6 5 4 3 2 1 0 Name C7 C6 C5 C4 C3 C2 C1...

Page 177 - A repetitive pattern from 1 to 32 bits in length

Product Preview DS21Q55 177 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 25. BERT FUNCTION The BERT (Bit Error Rate Tester) block can generate and detect both pseudorandom and repeating-bit patterns. It is used to test and stre...

Page 178 - BERT Register Description; BERT Control Register 1

Product Preview DS21Q55 178 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 25.1 BERT Register Description Register Name: BC1 Register Description: BERT Control Register 1 Register Address: E0h Bit # 7 6 5 4 3 2 1 0 Name TC TINV R...

Page 179 - BERT Control Register 2

Product Preview DS21Q55 179 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: BC2 Register Description: BERT Control Register 2 Register Address: E1h Bit # 7 6 5 4 3 2 1 0 Name EIB2 EIB1 EIB0 SBE RPL3 RPL2 RPL1 RPL0 D...

Page 180 - BIC

Product Preview DS21Q55 180 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: BIC Register Description: BER T Interface Control Register Register Address: EAh Bit # 7 6 5 4 3 2 1 0 Name - RFUS - TBAT TFUS - BERTDIR BE...

Page 181 - Status Register 9

Product Preview DS21Q55 181 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: SR9 Register Description: Status Register 9 Register Address: 2 6 h Bit # 7 6 5 4 3 2 1 0 Name - BBED BBCO BEC0 BRA1 BRA0 BRLOS BSYNC Defau...

Page 182 - Interrupt Mask Register 9

Product Preview DS21Q55 182 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: IMR9 Register Description: Interrupt Mask Register 9 Register Addres s : 2 7 h Bit # 7 6 5 4 3 2 1 0 Name - BBED BBCO BEC0 BRA1 BRA0 BRLOS ...

Page 183 - BERT Repetitive Pattern Set

Product Preview DS21Q55 183 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 25.2 BERT Repetitive Pattern Set These registers must be properly loaded for the BERT to generate and synchronize to a repetitive pattern, a pseudorandom ...

Page 184 - BERT Bit Counter; BERT Bit Count Register 1

Product Preview DS21Q55 184 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 25.3 BERT Bit Counter Once BERT has achieved synchronization, this 32-bit counter will increment for each data bit (i.e., clock) received. Toggling the LC...

Page 185 - BERT Error Counter; BERT Error Count Register 1

Product Preview DS21Q55 185 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 25.4 BERT Error Counter Once BERT has achieved synchronization, this 24-bit counter will increment for each data bit received in error. Toggling the LC co...

Page 186 - PAYLOAD ERROR INSERTION FUNCTION; Special Per-Channel Registration; TRANSMIT ERROR INSERTION SETUP SEQUENCE; STEP; or

Product Preview DS21Q55 186 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 26. PAYLOAD ERROR INSERTION FUNCTION An error- insertion function is available in the DS21Q55 and is used to create errors in the payload portion of the T...

Page 187 - ERC

Product Preview DS21Q55 187 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: ERC Register Description: Error Rate Control Register Register Address: EBh Bit # 7 6 5 4 3 2 1 0 Name WNOE - - CE ER3 ER2 ER1 ER0 Default ...

Page 188 - Number Of Error Registers; VALUE; Number Of Errors 1

Product Preview DS21Q55 188 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 26.1 Number Of Error Registers The number of error registers determine how many errors will be generated. Up to 1023 errors can be generated. The host wil...

Page 189 - Number Of Errors Left Register; Number Of Errors Left 1

Product Preview DS21Q55 189 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 26.1.1 Number Of Errors Left Register The host can read the NOELx registers at any time to determine how many errors are left to be inserted. Register Nam...

Page 190 - INTERLEAVED PCM BUS OPERATION

Product Preview DS21Q55 190 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 27. INTERLEAVED PCM BUS OPERATION In many architectures, the PCM outputs of individual framers are combined into higher speed PCM buses to simplify transp...

Page 191 - IBOC

Product Preview DS21Q55 191 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: IBOC Register Description: Interleave Bus Operation Control Register Register Address: C5h Bit # 7 6 5 4 3 2 1 0 Name - IBS1 IBS0 IBOSEL IB...

Page 192 - IBO EXAMPLE

Product Preview DS21Q55 192 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. IBO EXAMPLE Figure 29-1 RSYSCLK TSYSCLK RSYNC TSSYNC RSIG TSIG TSER RSER RSYSCLK TSYSCL K RSIG TSIG TSER RSER RSYSCLK TSYSCLK RSIG TSIG TSER RSER RSYSCLK ...

Page 193 - ESIB GROUP OF FOUR DS21Q55s

Product Preview DS21Q55 193 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 28. EXTENDED SYSTEM INFORMATION BUS (ESIB) The ESIB allows two DS21Q55s to share an 8-bit CPU bus for the purpose of reporting alarms and interrupt status...

Page 196 - Extended System Information Bus Register 1

Product Preview DS21Q55 196 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. Register Name: ESIB1 Register Description: Extended System Information Bus Register 1 Register Address: B2h Bit # 7 6 5 4 3 2 1 0 Name DISn DISn DISn DISn...

Page 197 - PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER; Common Control Register 2

Product Preview DS21Q55 197 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 29. PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER The DS21Q55 contains an on-chip clock synthesizer that generates a user-selectable clock referenced to the re...

Page 198 - Common Control Register 3

Product Preview DS21Q55 198 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 30. FRACTIONAL T1/E1 SUPPORT The DS21Q55 can be programmed to output gapped clocks for selected channels in the receive and transmit paths to simplify con...

Page 199 - JTAG FUNCTIONAL BLOCK DIAGRAM

Product Preview DS21Q55 199 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 31. JTAG -BOUNDARY-SCAN ARCHITECTURE AND TEST-ACCESS PORT The DS21Q55 is an MCM consisting of 4 DS2155s. Each device has its on JTAG state machine and the...

Page 200 - TAP Controller State Machine

Product Preview DS21Q55 200 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. TAP Controller State Machine The TAP controller is a finite state machine t hat responds to the logic level at JTMS on the rising edge of JTCLK (Figure 34...

Page 202 - TAP CONTROLLER STATE DIAGRAM

Product Preview DS21Q55 202 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. TAP CONTROLLER STATE DIAGRAM Figure 34-2 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 SelectDR-Scan Capture DR Shift DR Exit DR Pause DR ...

Page 203 - Instruction Register; INSTRUCTION

Product Preview DS21Q55 203 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 31.1 Instruction Register The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the TAP co...

Page 204 - BYPASS; ID CODE STRUCTURE; MSB; Device ID; DEVICE ID CODES; DEVICE

Product Preview DS21Q55 204 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. SAMPLE/P RELOAD This is a mandatory instruction for the IEEE 1149.1 specification that supports two functions. The digital I/Os of the device can be sampl...

Page 205 - Test Registers

Product Preview DS21Q55 205 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. DS21552 0002h 31.2 Test Registers IEEE 1149.1 requires a minimum of two test registers: the bypass register and the boundary scan register. An optional te...

Page 206 - BOUNDARY SCAN CONTROL BITS; NXA; = Not Externally Available; BIT

Product Preview DS21Q55 206 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. BOUNDARY SCAN CONTROL BITS Table 34-4 NXA = Not Externally Available BIT PIN SYMBOL TYPE CONTROL BIT DESCRIPTION 2 1 RCHBLK O 2 JTMS I 1 3 BPCLK O 4 JTCLK...

Page 208 - FUNCTIONAL TIMING DIAGRAMS

Product Preview DS21Q55 208 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. BIT PIN SYMBOL TYPE CONTROL BIT DESCRIPTION 7 97 RFSYNC O 6 – RSYNC.cntl – 0 = RSYNC is an input; 1 = RSYNC is an output 5 98 RSYNC I/O 4 99 RLOS/LOTC O 3...

Page 209 - RECEIVE SIDE ESF TIMING

Product Preview DS21Q55 209 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. RECEIVE SIDE ESF TIMING Figure 35-2 NOTES: 1) RSYNC in frame mode (IOCR1.4 = 0) and double wide frame sync is not enabled (IOCR1.6 = 0). 2) RSYNC in frame...

Page 210 - RECEIVE SIDE BOUNDARY TIMING (With Elastic Store Disabled); RCHBLK is programmed to block channel 24.

Product Preview DS21Q55 210 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. RECEIVE SIDE BOUNDARY TIMING (With Elastic Store Disabled) Figure 35-3 NOTES: 1) RCHBLK is programmed to block channel 24. 2) Shown is RLINK/RLCLK in the ...

Page 211 - RECEIVE SIDE 1.544MHz BOUNDARY TIMING

Product Preview DS21Q55 211 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. RECEIVE SIDE 1.544MHz BOUNDARY TIMING (With Elastic Store Enabled ) Figure 35-4 NOTES: 1) RSYNC is in the output mode (IOCR1.4 = 0). 2) RSYNC is in the in...

Page 212 - RECEIVE SIDE 2.048MHz BOUNDARY TIMING (With Elastic Store Enabled); RCHBLK is forced to one in the same channels as RSER (Note 1).

Product Preview DS21Q55 212 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. RECEIVE SIDE 2.048MHz BOUNDARY TIMING (With Elastic Store Enabled) Figure 35-5 NOTES: 1) RSER data in channels 1, 5, 9, 13, 17, 21, 25, and 29 are forced ...

Page 213 - TRANSMIT SIDE D4 TIMING

Product Preview DS21Q55 213 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. TRANSMIT SIDE D4 TIMING Figure 35-6 NOTES: 1) TSYNC in the frame mode (IOCR1.2 = 0) and double-wide frame sync is not enabled (IOCR1.1 = 0). 2) TSYNC in t...

Page 214 - TRANSMIT SIDE ESF TIMING

Product Preview DS21Q55 214 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. TRANSMIT SIDE ESF TIMING Figure 35-7 NOTES: 1) TSYNC in frame mode (IOCR1.2 = 0) and double -wide frame sync is not enabled (IOCR1.3 = 0). 2) TSYNC in fra...

Page 215 - TRANSMIT SIDE BOUNDARY TIMING (With Elastic Store Disabled); TCHBLK is programmed to block channel 2.

Product Preview DS21Q55 215 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. TRANSMIT SIDE BOUNDARY TIMING (With Elastic Store Disabled) Figure 35-8 NOTES: 1) TSYNC is in the output mode (IOCR1.1 = 1). 2) TSYNC is in the input mode...

Page 216 - TRANSMIT SIDE 1.544MHz BOUNDARY TIMING

Product Preview DS21Q55 216 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. TRANSMIT SIDE 1.544MHz BOUNDARY TIMING (With Elastic Store Enabled) Figure 35-9 NOTE: 1) TCHBLK is programmed to block channel 24 (if the TPCSI bit is set...

Page 218 - RLINK

Product Preview DS21Q55 218 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 32.2 E1 Mode RECEIVE SIDE TIMING Figure 35-11 NOTES: 1) RSYNC in frame mode (IOCR1.5 = 0). 2) RSYNC in multiframe mode (IOCR1.5 = 1). 3) RLCLK is programm...

Page 219 - RCHBLK is programmed to block channel 1.

Product Preview DS21Q55 219 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. RECEIVE SIDE BOUNDARY TIMING (With Elastic Store Disabled) Figure 35-12 NOTES: 1) RCHBLK is programmed to block channel 1. 2) RLCLK is programmed to mark ...

Page 222 - RECEIVE IBO CHANNEL INTERLEAVE MODE TIMING

Product Preview DS21Q55 222 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. RECEIVE IBO CHANNEL INTERLEAVE MODE TIMING Figure 35-15 NOTES: 1) 4.096MHz bus configuration. 2) 8.192MHz bus configuration. 3) 16.384MHz bus configuratio...

Page 223 - RECEIVE IBO FRAME INTERLEAVE MODE TIMING

Product Preview DS21Q55 223 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. RECEIVE IBO FRAME INTERLEAVE MODE TIMING Figure 35-16 NOTES: 1) 4.096MHz bus configuration. 2) 8.192MHz bus configuration. 3) 16.384MHz bus configuration ...

Page 225 - TRANSMIT SIDE TIMING; TLINK is programmed to source just the Sa4 bit.; TSSYNC

Product Preview DS21Q55 225 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. TRANSMIT SIDE TIMING Figure 35-18 NOTES: 1) TSYNC in frame mode (IOCR1.2 = 0). 2) TSYNC in multiframe mode (IOCR1.2 = 1). 3) TLINK is programmed to source...

Page 226 - TRANSMIT SIDE BOUNDARY TIMING

Product Preview DS21Q55 226 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. TRANSMIT SIDE BOUNDARY TIMING (With Elastic Store Disabled) Figure 35-19 NOTES: 1) TSYNC is in the output mode (IOCR1.1 = 1.) 2) TSYNC is in the input mod...

Page 227 - TSYSCLK

Product Preview DS21Q55 227 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. TRANSMIT SIDE BOUNDARY TIMING, TSYSCLK = 1.544MHz (With Elastic Store Enabled) Figure 35-20 NOTES: 1) The F-bit position in the TSER data is ignored. 2) T...

Page 229 - TRANSMIT IBO CHANNEL INTERLEAVE MODE TIMING; TSYNC is in input mode

Product Preview DS21Q55 229 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. TRANSMIT IBO CHANNEL INTERLEAVE MODE TIMING Figure 35-22 NOTES: 1) 4.096MHz bus configuration. 2) 8.192MHz bus configuration. 3) 16.384MHz bus configurati...

Page 230 - TRANSMIT IBO FRAME INTERLEAVE MODE TIMING

Product Preview DS21Q55 230 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. TRANSMIT IBO FRAME INTERLEAVE MODE TIMING Figure 35-23 NOTES: 1) 4.096MHz bus configuration. 2) 8.192MHz bus configuration. 3) 16.384MHz bus configuration...

Page 231 - OPERATING PARAMETERS

Product Preview DS21Q55 231 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 33. OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS* Voltage Range on Any Pin Relative to Ground -1.0V to +6.0V Operating Temperature Range for DS21Q55 0 ° ...

Page 232 - RECOMMENDED DC OPERATING CONDITIONS

Product Preview DS21Q55 232 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. RECOMMENDED DC OPERATING CONDITIONS (0 ° C to +70 ° C for DS21Q55; -40 ° C to +85 ° C for DS21Q55N) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Logic 1 V IH ...

Page 233 - AC TIMING PARAMETERS AND DIAGRAMS

Product Preview DS21Q55 233 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 34. AC TIMING PARAMETERS AND DIAGRAMS Capacitive test loads are 40pF for bus signals, 20pF for all others. 34.1 Multipexed Bus AC Characteristics AC CHARA...

Page 236 - Nonmultiplexed Bus AC Characteristics

Product Preview DS21Q55 236 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 34.2 Nonmultiplexed Bus AC Characteristics AC CHARACTERISTICS–NONMULTIPLEXED PARALLEL PORT (MUX = 0) (0 ° C to +70 ° C; V DD = 3.3V ± 5% for DS21Q55; -40 ...

Page 237 - Address Valid

Product Preview DS21Q55 237 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. INTEL BUS READ TIMING (BTS = 0 / MUX = 0) Figure 37-4 INTEL BUS WRITE TIMING (BTS = 0 / MUX = 0) Figure 37-5 Address Valid Data Valid A0 to A7 D0 to D7 WR...

Page 239 - Receive Side AC Characteristics

Product Preview DS21Q55 239 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 34.3 Receive Side AC Characteristics AC CHARACTERISTICS–RECEIVE SIDE (0 ° C to +70 ° C; V DD = 3.3V ± 5% for DS21Q55; - 40 ° C to +85 ° C; V DD = 3.3V ± 5...

Page 242 - RECEIVE LINE INTERFACE TIMING

Product Preview DS21Q55 242 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. RECEIVE LINE INTERFACE TIMING Figure 37-10 t F t R RPOSI, RNEGI RCLKI CL t t CP CH t t SU t HD t DD RPOSO, RNEGO RCLKO LL t t LP LH t

Page 243 - Transmit AC Characteristics

Product Preview DS21Q55 243 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 34.4 Transmit AC Characteristics AC CHARACTERISTICS–TRANSMIT SIDE (0 ° C to +70 ° C; V DD = 3.3V ± 5% for DS21Q55; -40 ° C to +85 ° C; V DD = 3.3V ± 5% fo...

Page 245 - TRANSMIT SIDE TIMING, EL ASTIC STORE ENABLED

Product Preview DS21Q55 245 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. TRANSMIT SIDE TIMING, EL ASTIC STORE ENABLED Figure 37-12 t F t R TSYSCLK TSER TCHCLK t t SL t SH SP TSSYNC TCHBLK t D3 t D3 t t t SU HD SU t HD NOTES: 1)...

Page 246 - TRANSMIT LINE INTERFACE TIMING

Product Preview DS21Q55 246 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. TRANSMIT LINE INTERFACE TIMING Figure 37-13 TCLKO TPOSO, TNEGO t DD t F t R TCLKI TPOSI, TNEGI t t LL t LH LP t HD t SU

Page 247 - MECHANICAL DESCRIPTIONS

Product Preview DS21Q55 247 o f 248 012103 Please contact [email protected] or search http://www.maxim -ic.com for updated information. 35. MECHANICAL DESCRIPTIONS