Page 2 - DS33Z41 Quad IMUX Ethernet Mapper; TABLE OF CONTENTS; SDRAM I
DS33Z41 Quad IMUX Ethernet Mapper 2 of 167 TABLE OF CONTENTS 1 DESCRIPTION ....................................................................................................................7 2 FEATURE HIGHLIGHTS .........................................................................................
Page 4 - JTAG ID C
DS33Z41 Quad IMUX Ethernet Mapper 4 of 167 12.2.2 BYPASS ............................................................................................................................................163 12.2.3 EXTEST ........................................................................................
Page 5 - LIST OF FIGURES
DS33Z41 Quad IMUX Ethernet Mapper 5 of 167 LIST OF FIGURES Figure 3-1. Quad T1/E1 SCT to DS33Z41 .............................................................................................................. 11 Figure 6-1. Detailed Block Diagram..........................................................
Page 6 - LIST OF TABLES
DS33Z41 Quad IMUX Ethernet Mapper 6 of 167 LIST OF TABLES Table 2-1. T1 Related Telecommunications Specifications .................................................................................... 10 Table 7-1. Detailed Pin Descriptions ................................................................
Page 7 - DESCRIPTION; Unframed T1/E1 WAN Bridge
DS33Z41 Quad IMUX Ethernet Mapper 7 of 167 1 DESCRIPTION The DS33Z41 provides interconnection and mapping functionality between Ethernet Packet Systems and WAN Time-Division Multiplexed (TDM) systems such as T1/E1/J1, HDSL, and T3/E3. The device is composed of a 10/100 Ethernet MAC, Packet Arbiter, ...
Page 8 - Aggregation
DS33Z41 Quad IMUX Ethernet Mapper 8 of 167 2 FEATURE HIGHLIGHTS 2.1 General • 169-pin, 14mm x 14mm CSBGA package • 1.8V supply with 3.3V tolerant inputs and outputs • IEEE 1149.1 JTAG boundary scan • Software access to device ID and silicon revision • Development support includes evaluation kit, dri...
Page 10 - Specifications compliance; CSMA/CD access method and physical layer specifications
DS33Z41 Quad IMUX Ethernet Mapper 10 of 167 2.10 Specifications compliance The DS33Z41 meets relevant telecommunications specifications. The following table provides the specifications and relevant sections that are applicable to the DS33Z41. Table 2-1. T1 Related Telecommunications Specifications I...
Page 11 - APPLICATIONS; Bonded Transparent LAN Service
DS33Z41 Quad IMUX Ethernet Mapper 11 of 167 3 APPLICATIONS • Bonded Transparent LAN Service • LAN Extension • Ethernet Delivery Over T1/E1/J1, T3/E3, OC-1/EC-1, G.SHDSL, or HDSL2/4 Refer also to Application Note 3411: DS33Z11—Ethernet LAN to Unframed T1/E1 WAN Bridge for an example of a complete LAN...
Page 12 - TIME SLOT NUMBERING SCHEMES; Time Slot
DS33Z41 Quad IMUX Ethernet Mapper 12 of 167 4 ACRONYMS AND GLOSSARY • BERT—Bit Error Rate Tester • DCE—Data Communication Interface • DTE—Data Terminating Interface • FCS—Frame Check Sequence • HDLC—High Level Data Link Control • MAC—Media Access Control • MII—Media Independent Interface • RMII—Redu...
Page 13 - MAJOR OPERATING MODES
DS33Z41 Quad IMUX Ethernet Mapper 13 of 167 5 MAJOR OPERATING MODES Operation of the DS33Z41 operation requires a host microprocessor for initialization and maintenance of the link aggregation functions. Microprocessor control is possible through the 8-bit parallel control port. More information on ...
Page 14 - PIN DESCRIPTIONS; Pin Functional Description; RST
DS33Z41 Quad IMUX Ethernet Mapper 14 of 167 7 PIN DESCRIPTIONS 7.1 Pin Functional Description Note that all digital pins are inout pins in JTAG mode. This feature increases the effectiveness of board level ATPG patterns. Table 7-1. Detailed Pin Descriptions Note: I = Input; O = Output; Ipu = Input w...
Page 18 - SRAS
DS33Z41 Quad IMUX Ethernet Mapper 18 of 167 NAME PIN TYPE FUNCTION SDRAM CONTROLLER SDATA[0] SDATA[1] SDATA[2] SDATA[3] SDATA[4] SDATA[5] SDATA[6] SDATA[7] SDATA[8] SDATA[9] SDATA[10] SDATA[11] SDATA[12] SDATA[13] SDATA[14] SDATA[15] SDATA[16] SDATA[17] SDATA[18] SDATA[19] SDATA[20] SDATA[21] SDATA[...
Page 20 - NAME PIN; VSS; VSS: Connect to the Common Supply Ground; Do not connect these pins.
DS33Z41 Quad IMUX Ethernet Mapper 20 of 167 NAME PIN TYPE FUNCTION POWER SUPPLIES VDD3.3 G5–G10, H2, H5, H6, H7–H10 I VDD3.3: Connect to 3.3V Power Supply VDD1.8 D3, D2, E3, F4, J4, K4, L3, F10, E11, E12, D12, M13, L12 I VDD1.8: Connect to 1.8V Power Supply VSS A9, A12, B10, C10, D1, D5, E7, E8, F6,...
Page 22 - FUNCTIONAL
DS33Z41 Quad IMUX Ethernet Mapper 22 of 167 8 FUNCTIONAL DESCRIPTION The DS33Z41 provides interconnection and mapping functionality between Ethernet Packet Systems and WAN Time-Division Multiplexed (TDM) systems such as T1/E1/J1, HDSL, and T3/E3. The device is composed of a 10/100 Ethernet MAC, Pack...
Page 23 - Interface
DS33Z41 Quad IMUX Ethernet Mapper 23 of 167 8.1 Processor Interface Microprocessor control of the DS33Z41 is accomplished through the 20 interface pins of the microprocessor port. The 8-bit parallel data bus can be configured for Intel or Motorola modes of operation with the two MODEC[1:0] pins. Whe...
Page 24 - Structure
DS33Z41 Quad IMUX Ethernet Mapper 24 of 167 8.2 Clock Structure The DS33Z41 clocks sources and functions are as follows: • Serial Transmit Data (TCLKI) and Serial Receive Data (RCLKI) clock inputs are used to transfer data from the serial interface. These clocks can be gapped. • System Clock (SYSCLK...
Page 28 - Initialization and Configuration; EXAMPLE DEVICE INITIALIZATION SEQUENCE:; Resources
DS33Z41 Quad IMUX Ethernet Mapper 28 of 167 8.4 Initialization and Configuration EXAMPLE DEVICE INITIALIZATION SEQUENCE: STEP 1: Reset the device by pulling the RST pin low or by using the software reset bits outlined in Section 8.3 . Clear all reset bits. Allow 5 milliseconds for the reset recovery...
Page 29 - Interrupts
DS33Z41 Quad IMUX Ethernet Mapper 29 of 167 8.7 Device Interrupts Figure 8-2 diagrams the flow of interrupt conditions from their source status bits through the multiple levels of information registers and mask bits to the interrupt pin. When an interrupt occurs, the host can read the Global Latched...
Page 30 - Figure 8-2. Device Interrupt Information Flow Diagram; Interrup
DS33Z41 Quad IMUX Ethernet Mapper 30 of 167 Figure 8-2. Device Interrupt Information Flow Diagram Receive FCS Errored Packet 7 Receive Aborted Packet 6 Receive Invalid Packet Detected 5 Receive Small Packet Detected 4 Receive Large Packet Detected 3 Receive FCS Errored Packet Count 2 Receive Aborted...
Page 31 - and
DS33Z41 Quad IMUX Ethernet Mapper 31 of 167 8.8 Serial Interface The Serial Interface consists of physical serial port, IMUX/IBO Formatter, and HDLC/X.86 engine. The Serial Interface supports time-division multiplexed serial data, in a format compatible with Dallas Semiconductor’s 8.192Mbps Channel ...
Page 32 - Figure 8-4. Diagram of Data Transmission with IMUX Operation
DS33Z41 Quad IMUX Ethernet Mapper 32 of 167 Figure 8-3. IMUX Interface to T1/E1 Transceivers T1E1 T1E1 T1E1 T1E1 LIU LIU LIU LIU Framer Framer Framer Framer I B O TSER RSER TSYNC RSYNC Line 1 IMUX Ethernet Port Arbiter SDRAM Interface HD L C T1E1 T1E1 TCLKI RCLKI Figure 8-4. Diagram of Data Transmis...
Page 33 - Requirements
DS33Z41 Quad IMUX Ethernet Mapper 33 of 167 8.9.1 Microprocessor Requirements Link aggregation requires an external host microprocessor to issue instructions and to monitor the IMUX function of the DS33Z41. The host microprocessor is responsible for the following tasks to open a transmit channel: • ...
Page 34 - Figure 8-5. Command Structure for IMUX Function; Table 8-3. Commands Sent and Received on the IMUX Links; COMMAND
DS33Z41 Quad IMUX Ethernet Mapper 34 of 167 8.9.2 IMUX Command Protocol The format for all commands sent and received in Channel 2 of the IBO Serial Interface is shown in Figure 8-5 . The MSB for all commands is a “1”. The next 6 bits contain the actual opcode for the command. The LSB is the even pa...
Page 35 - REGISTER NAME COMMENTS
DS33Z41 Quad IMUX Ethernet Mapper 35 of 167 The command and status registers for the IMUX function are detailed below: Table 8-4. Command and Status for the IMUX for Processor Communication REGISTER NAME COMMENTS IMUX Configuration Register GL.IMXCN Used to configure the number of links participatin...
Page 36 - Transfer
DS33Z41 Quad IMUX Ethernet Mapper 36 of 167 8.9.3 Out of Frame (OOF) Monitoring Once the links are in synchronization, frame synchronization monitoring is started. The device will declare an out of frame (OOF) if 2 consecutive sequence errors are received. The device automatically adjusts for single...
Page 37 - Connections and Queues; size
DS33Z41 Quad IMUX Ethernet Mapper 37 of 167 8.10 Connections and Queues The multi-port devices in this product family provide bidirectional cross-connections between the multiple Ethernet ports and Serial ports when operating in software mode. A single connection is preserved in this single-port dev...
Page 38 - Table 8-5. Registers Related to Connections and Queues; REGISTER FUNCTION
DS33Z41 Quad IMUX Ethernet Mapper 38 of 167 It is recommended that the user reset the queue pointers for the connection after disconnection. The pointers must be reset before a connection is made. If this disconnect/connect procedure is not followed, incorrect data may be transmitted. The proper pro...
Page 39 - OPTION MODE
DS33Z41 Quad IMUX Ethernet Mapper 39 of 167 8.12 Flow Control Flow control may be required to ensure that data queues do not overflow and packets are not lost. The DS33Z41 allows for optional flow control based on the queue high watermark or through host processor intervention. There are 2 basic mec...
Page 41 - Figure 8-6. Flow Control Using Pause Control Frame; bit is set. If the queue remains above the high threshold,
DS33Z41 Quad IMUX Ethernet Mapper 41 of 167 Figure 8-6. Flow Control Using Pause Control Frame Receive Queue Growth Receive Queue High Water Mark Initiate Flow control 8 Rx Data Receive Queue Low Water 8.12.2 Half-Duplex Flow control Half duplex flow control uses a jamming sequence to exert backpres...
Page 42 - Ethernet Interface Port; behavior and should be avoided.
DS33Z41 Quad IMUX Ethernet Mapper 42 of 167 8.13 Ethernet Interface Port The Ethernet port interface allows for direct connection to an Ethernet PHY. The interface consists of a 10/100Mbps MII/RMII interface and an Ethernet MAC. In RMII operation, the interface contains 7 signals with a reference cl...
Page 43 - Table 8-7. Registers Related to the Ethernet Port
DS33Z41 Quad IMUX Ethernet Mapper 43 of 167 • MII error asserted during the reception of the frame. • Dribbling bits occurred in the frame. • CRC error occurred. • Length error occurred—the length indicated by the frame length is inconsistent with the number of bytes received. • Control frame was re...
Page 44 - DCE
DS33Z41 Quad IMUX Ethernet Mapper 44 of 167 Figure 8-8. Configured as DTE Connected to an Ethernet PHY in MII Mode MAC RXD[3:0] RXD[3:0] RX_CLK RX_CLK RX_ERR RX_ERR RX_CRS RX_CRS COL_DET COL_DET Ethernet Phy TX_EN TX_EN MDC MDIO TXD[3:0] TXD[3:0] TX_CLK DS33Z41 WAN DCE DTE TX_CLK MDIO MDC RXDV RXDV ...
Page 45 - Figure 8-9. DS33Z41 Configured as a DCE in MII Mode
DS33Z41 Quad IMUX Ethernet Mapper 45 of 167 Figure 8-9. DS33Z41 Configured as a DCE in MII Mode MAC TXD[3:0] RXD[3:0] TX_CLK RX_CLK TX_ERR RX_ERR TX_EN RX_CRS COL_DET COL_DET DTE DCE TX_EN RXDV MDC MDIO TXD[3:0] RXD[3:0] TX_CLK DS33Z41 WAN MAC RX_CLK RXDV RX_CRS MDIO MDC Rx Tx Tx Rx Arbiter
Page 48 - PHY MII Management Block and MDIO Interface; BERT will transmit even when the device is set for X.86 mode.
DS33Z41 Quad IMUX Ethernet Mapper 48 of 167 8.14.3 PHY MII Management Block and MDIO Interface The MII Management Block allows for the host to control up to 32 PHYs, each with 32 registers. The MII block communicates with the external PHY using 2-wire serial interface composed of MDC (serial clock) ...
Page 49 - Figure 8-12. PRBS Synchronization State Diagram; Sync; Repetitive Pattern Synchronization
DS33Z41 Quad IMUX Ethernet Mapper 49 of 167 8.15.2 Receive Data Interface 8.15.2.1 Receive Pattern Detection The Receive BERT receives only the payload data and synchronizes the receive pattern generator to the incoming pattern. The receive pattern generator is a 32-bit shift register that shifts da...
Page 50 - Figure 8-13. Repetitive Pattern Synchronization State Diagram; the seed value is all ones.
DS33Z41 Quad IMUX Ethernet Mapper 50 of 167 Figure 8-13. Repetitive Pattern Synchronization State Diagram Sync Match Verify 1 bit error Pattern Matches 32 b its w ith ou t e rr or s 6 o f 6 4 b its w ith er ro rs 8.15.4 Pattern Monitoring Pattern monitoring monitors the incoming data stream for Out ...
Page 52 - Transmit Packet Processor; The packet scrambler is a x
DS33Z41 Quad IMUX Ethernet Mapper 52 of 167 8.16 Transmit Packet Processor The Transmit Packet Processor accepts data from the Transmit FIFO performs bit reordering, FCS processing, packet error insertion, stuffing, packet abort sequence insertion, inter-frame padding, and packet scrambling. The dat...
Page 53 - Receive Packet Processor; The packet descrambler is a self-synchronous x
DS33Z41 Quad IMUX Ethernet Mapper 53 of 167 8.17 Receive Packet Processor The Receive Packet Processor accepts data from the Receive Serial Interface performs packet descrambling, packet delineation, inter-frame fill filtering, packet abort detection, destuffing, packet size checking, FCS error moni...
Page 55 - Figure 8-14. LAPS Encoding of MAC Frames Concept
DS33Z41 Quad IMUX Ethernet Mapper 55 of 167 8.18 X.86 Encoding and Decoding X.86 protocol provides a method for encapsulating Ethernet Frame onto LAPS. LAPS provides a HDLC-type framing structure for encapsulation of Ethernet frames, but does not inflict dynamic bandwidth expansion as HDLC does. LAP...
Page 58 - Committed Information Rate Controller; . The CIR will restrict the data flow
DS33Z41 Quad IMUX Ethernet Mapper 58 of 167 8.19 Committed Information Rate Controller The DS33Z41 provides a CIR provisioning facility. The CIR can be used to restrict the transport of received MAC data to the serial port at a programmable rate. This is shown in Figure 8-16 . The CIR will restrict ...
Page 59 - Figure 8-16. CIR in the WAN Transmit Path
DS33Z41 Quad IMUX Ethernet Mapper 59 of 167 Figure 8-16. CIR in the WAN Transmit Path MAC RMII MII SDRAM Interface Buffer Dev Div by 2,4,12 Output Clocks 25,50 Mhz 100 Mhz Oscillator SYSCLKI SDCLKO Buffer Dev Div by 1,2,4,8,10 Output clocks: 50,25 Mhz,2.5 Mhz 50 or 25 Mhz Oscillator TX_CLK1 RX_CLK1 ...
Page 60 - DEVICE; Ten address lines are used to address the register space.
DS33Z41 Quad IMUX Ethernet Mapper 60 of 167 9 DEVICE REGISTERS Ten address lines are used to address the register space. Table 9-1 shows the register map for the DS33Z41. The addressable range for the device is 0000h to 08FFh. Each Register Section is 64 bytes deep. Global Registers are preserved fo...
Page 61 - Bit; contain the registers of the DS33Z41. Bits; Name B
DS33Z41 Quad IMUX Ethernet Mapper 61 of 167 9.1 Register Bit Maps Table 9-2 , Table 9-3 , Table 9-4 , Table 9-5 , Table 9-6 , and Table 9-7 contain the registers of the DS33Z41. Bits that are reserved are noted with a single dash “-“. All registers not listed are reserved and should be initialized w...
Page 63 - Serial Interface Register Bit Map; Table 9-5. Serial Interface Register Bit Map
DS33Z41 Quad IMUX Ethernet Mapper 63 of 167 9.1.4 Serial Interface Register Bit Map Table 9-5. Serial Interface Register Bit Map A DDR N AME B IT 7 B IT 6 B IT 5 B IT 4 B IT 3 B IT 2 B IT 1 B IT 0 0C0h Reserved - - - - - - - - 0C1h LI.RSTPD - - - - - - RESET - 0C2h LI.LPBK - - - - - - - QLP 0C3h Res...
Page 65 - Ethernet Interface Register Bit Map; Table 9-6. Ethernet Interface Register Bit Map
DS33Z41 Quad IMUX Ethernet Mapper 65 of 167 9.1.5 Ethernet Interface Register Bit Map Table 9-6. Ethernet Interface Register Bit Map A DDR N AME B IT 7 B IT 6 B IT 5 B IT 4 B IT 3 B IT 2 B IT 1 B IT 0 140h SU.MACRADL MACRA7 MACRA6 MACRA5 MACRA4 MACRA3 MACRA2 MACRA1 MACRA0 141h SU.MACRADH MACRA15 MAC...
Page 66 - Table 9-7. MAC Indirect Register Bit Map
DS33Z41 Quad IMUX Ethernet Mapper 66 of 167 9.1.6 MAC Register Bit Map Table 9-7. MAC Indirect Register Bit Map A DDR N AME B IT 7 B IT 6 B IT 5 B IT 4 B IT 3 B IT 2 B IT 1 B IT 0 0000h SU.MACCR 31:24 - - - HDB PS - - - 0001h 23:16 DRO OML1 OML0 F PM PAM - - 0002h 15:8 - - - LCC - DRTY - ASTP 0003h ...
Page 68 - Global Register Definitions; Global ID Low Register
DS33Z41 Quad IMUX Ethernet Mapper 68 of 167 9.2 Global Register Definitions Functions contained in the global registers include: framer reset, LIU reset, device ID, BERT interrupt status, framer interrupt status, IBO configuration, MCLK configuration, and BPCLK configuration. These registers are pre...
Page 69 - Global Control Register 1; INT; Global BERT Connect Register
DS33Z41 Quad IMUX Ethernet Mapper 69 of 167 Register Name: GL.CR1 Register Description: Global Control Register 1 Register Address: 02h Bit # 7 6 5 4 3 2 1 0 Name — — — — — REF_CLKO INTM RST Default 0 0 0 Bit 2: REF_CLKO OFF (REF_CLKO). This bit determines the REF_CLKO output mode. 1 = REF_CLKO is d...
Page 70 - Global SDRAM Reference Clock Activity Latched Status
DS33Z41 Quad IMUX Ethernet Mapper 70 of 167 Register Name: GL.RTCAL Register Description: Global Receive and Transmit Serial Port Clock Activity Latched Status Register Address: 04h Bit # 7 6 5 4 3 2 1 0 Name — — — RLCALS1 — — — TLCALS1 Default 0 0 0 0 0 0 0 0 Bit 4: Receive Serial Interface Clock A...
Page 77 - Inverse MUX OOF Interrupt Enable
DS33Z41 Quad IMUX Ethernet Mapper 77 of 167 Register Name: GL.IMXOOFIE Register Description: Inverse MUX OOF Interrupt Enable Register Address: 1Eh Bit # 7 6 5 4 3 2 1 0 Name TOOFIE4 TOOFIE3 TOOFIE2 TOOFIE1 ROOFIE4 ROOFIE3 ROOFIE2 ROOFIE1 Default 0 0 0 0 0 0 0 0 Bit 7: IMUX Transmit OOF Interrupt En...
Page 80 - Global SDRAM Refresh Time Control
DS33Z41 Quad IMUX Ethernet Mapper 80 of 167 Register Name: GL.SDRFTC Register Description Global SDRAM Refresh Time Control Register Address: 3Dh Bit # 7 6 5 4 3 2 1 0 Name SREFT7 SREFT6 SREFT5 SREFT4 SREFT3 SREFT2 SREFT1 SREFT0 Default 0 1 0 0 0 1 1 0 Bits 7 to 0: SDRAM Refresh Time Control (SREFT7...
Page 81 - Registers; Arbiter Register Bit Descriptions; Arbiter Receive Queue Size Connection; These 7 bits of the size of receive queue associated with; Note: Queue size of 0 is not allowed and should never be set.; Register Description:; Arbiter Transmit Queue Size Connection 1; This is size of transmit queue associated with the; Note that queue size of 0 is not allowed and should never be set.
DS33Z41 Quad IMUX Ethernet Mapper 81 of 167 9.3 Arbiter Registers The Arbiter manages the transport between the Ethernet port and the Serial Interface. It is responsible for queuing and dequeuing data to an external SDRAM. The arbiter handles requests from the HDLC and MAC to transfer data to/from t...
Page 82 - BCR
DS33Z41 Quad IMUX Ethernet Mapper 82 of 167 9.4 BERT Registers Register Name: BCR Register Description: BERT Control Register Register Address: 80h Bit # 7 6 5 4 3 2 1 0 Name — PMU RNPL RPIC MPR APRD TNPL TPIC Default 0 0 0 0 0 0 0 0 Bit 7: This bit must be kept low for proper operation. Bit 6: Perf...
Page 88 - Receive Bit Count Byte 1 Register #1; Receive Bit Count Byte 2 Register; Receive Bit Count Byte 3 Register
DS33Z41 Quad IMUX Ethernet Mapper 88 of 167 Register Name: RBCB1 Register Description: Receive Bit Count Byte 1 Register #1 Register Address: 99h Bit # 7 6 5 4 3 2 1 0 Name BC15 BC14 BC13 BC12 BC11 BC10 BC9 BC8 Default 0 0 0 0 0 0 0 0 Bits 7 to 0: Bit Count (BC15 to BC8). Eight bits of a 32-bit valu...
Page 89 - Serial Interface Registers; Serial Interface Transmit and Common Registers; Serial Interface Reset Register
DS33Z41 Quad IMUX Ethernet Mapper 89 of 167 9.5 Serial Interface Registers The Serial Interface contains the Serial HDLC transport circuitry and the associated serial port. The Serial Interface register map consists of registers that are common functions, transmit functions, and receive functions. B...
Page 90 - Transmit HDLC Processor Registers; Transmit Packet Processor Control Low Register
DS33Z41 Quad IMUX Ethernet Mapper 90 of 167 9.5.3 Transmit HDLC Processor Registers Register Name: LI.TPPCL Register Description: Transmit Packet Processor Control Low Register Register Address: 0C4h Bit # 7 6 5 4 3 2 1 0 Name — — TFAD TF16 TIFV TSD TBRE TIAEI Default 0 0 0 0 0 0 0 0 Note: The user ...
Page 91 - Transmit Inter-Frame Gapping Control Register; These eight bits indicate the number of additional; Transmit Errored Packet Low Control Register; These eight bits indicate the total
DS33Z41 Quad IMUX Ethernet Mapper 91 of 167 Register Name: LI.TIFGC Register Description: Transmit Inter-Frame Gapping Control Register Register Address: 0C5h Bit # 7 6 5 4 3 2 1 0 Name TIFG7 TIFG6 TIFG5 TIFG4 TIFG3 TIFG2 TIFG1 TIFG0 Default 0 0 0 0 0 0 0 1 Bits 7 to 0: Transmit Inter-Frame Gapping ...
Page 97 - X.86 Encoding Decoding Enable
DS33Z41 Quad IMUX Ethernet Mapper 97 of 167 9.5.4 X.86 Registers X.86 Transmit and common Registers are used to control the operation of the X.86 encoder and decoder. Register Name: LI.TX86EDE Register Description: X.86 Encoding Decoding Enable Register Address: 0D8h Bit # 7 6 5 4 3 2 1 0 Name — — —...
Page 101 - Receive Packet Processor Status Register Latched
DS33Z41 Quad IMUX Ethernet Mapper 101 of 167 Register Name: LI.RPPSRL Register Description: Receive Packet Processor Status Register Latched Register Address: 105h Bit # 7 6 5 4 3 2 1 0 Name REPL RAPL RIPDL RSPDL RLPDL REPCL RAPCL RSPCL Default — — — — — — — — Bit 7: Receive FCS Errored Packet Latch...
Page 102 - Receive Packet Processor Status Register Interrupt Enable
DS33Z41 Quad IMUX Ethernet Mapper 102 of 167 Register Name: LI.RPPSRIE Register Description: Receive Packet Processor Status Register Interrupt Enable Register Address: 106h Bit # 7 6 5 4 3 2 1 0 Name REPIE RAPIE RIPDIE RSPDIE RLPDIE REPCIE RAPCIE RSPCIE Default 0 0 0 0 0 0 0 0 Bit 7: Receive FCS Er...
Page 103 - Receive Packet Count Byte 0 Register; Receive Packet Count Byte 1 Register; Receive Packet Count Byte 2 Register; These 24 bits indicate the number of packets stored in
DS33Z41 Quad IMUX Ethernet Mapper 103 of 167 Register Name: LI.RPCB0 Register Description: Receive Packet Count Byte 0 Register Register Address: 108h Bit # 7 6 5 4 3 2 1 0 Name RPC7 RPC6 RPC5 RPC4 RPC3 RPC2 RPC1 RPC0 Default 0 0 0 0 0 0 0 0 Bits 7 to 0: Receive Packet Count (RPC7 to RPC0). Eight bi...
Page 104 - Receive FCS Errored Packet Count Byte 0 Register; Receive FCS Errored Packet Count Byte 1 Register; Receive FCS Errored Packet Count Byte 2 Register; These 24 bits indicate the number of
DS33Z41 Quad IMUX Ethernet Mapper 104 of 167 Register Name: LI.RFPCB0 Register Description: Receive FCS Errored Packet Count Byte 0 Register Register Address: 10Ch Bit # 7 6 5 4 3 2 1 0 Name RFPC7 RFPC6 RFPC5 RFPC4 RFPC3 RFPC2 RFPC1 RFPC0 Default 0 0 0 0 0 0 0 0 Bits 7 to 0: Receive FCS Errored Pack...
Page 106 - Receive Size Violation Packet Count Byte 0 Register; Receive Size Violation Packet Count Byte 1 Register; Receive Size Violation Packet Count Byte 2 Registers
DS33Z41 Quad IMUX Ethernet Mapper 106 of 167 Register Name: LI.RSPCB0 Register Description: Receive Size Violation Packet Count Byte 0 Register Register Address: 114h Bit # 7 6 5 4 3 2 1 0 Name RSPC7 RSPC6 RSPC5 RSPC4 RSPC3 RSPC2 RSPC1 RSPC0 Default 0 0 0 0 0 0 0 0 Bits 7 to 0: Receive Size Violatio...
Page 112 - Ethernet Interface Registers; Ethernet Interface Register Bit Descriptions; MAC Read Address Low Register
DS33Z41 Quad IMUX Ethernet Mapper 112 of 167 9.6 Ethernet Interface Registers The Ethernet Interface registers are used to configure RMII/MII bus operation and establish the MAC parameters as required by the user. The MAC Registers cannot be addressed directly from the Processor port. The registers ...
Page 120 - Receive Frame Status Byte 3
DS33Z41 Quad IMUX Ethernet Mapper 120 of 167 Register Name: SU.RFSB3 Register Description: Receive Frame Status Byte 3 Register Address: 157h Bit # 7 6 5 4 3 2 1 0 Name MF — — BF MCF UF CF LE Default 0 0 0 0 0 0 0 0 Bit 7: Missed Frame (MF). This bit is set to 1 if the packet is not successfully rec...
Page 123 - Receive Frame Rejection Control
DS33Z41 Quad IMUX Ethernet Mapper 123 of 167 Register Name: SU.RFRC Register Description: Receive Frame Rejection Control Register Address: 15Eh Bit # 7 6 5 4 3 2 1 0 Name — UCFR CFRR LERR CRCERR DBR MIIER BFR Default 0 0 0 0 0 0 0 0 Bit 6: Uncontrolled Control Frame Reject (UCFR). When set to 1, Co...
Page 124 - MAC Control Register
DS33Z41 Quad IMUX Ethernet Mapper 124 of 167 9.6.2 MAC Registers The control registers related to the control of the individual MACs are shown in the following tables. The DS33Z41 keeps statistics for the packet traffic sent and received. The register address map is shown in the following Table. Not...
Page 127 - MAC MII Management (MDIO) Address Register
DS33Z41 Quad IMUX Ethernet Mapper 127 of 167 Register Name: SU.MACMIIA Register Description: MAC MII Management (MDIO) Address Register Register Address: 0014h (indirect) 0014h: Bit # 31 30 29 28 27 26 25 24 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default 0 0 0 0...
Page 129 - MAC Flow Control Register
DS33Z41 Quad IMUX Ethernet Mapper 129 of 167 Register Name: SU.MACFCR Register Description: MAC Flow Control Register Register Address: 001Ch (indirect) 001Ch: Bit # 31 30 29 28 27 26 25 24 Name PT15 PT14 PT13 PT12 PT11 PT10 PT09 PT08 Default 0 0 0 0 0 0 0 0 001Dh: Bit # 23 22 21 20 19 18 17 16 Name...
Page 130 - MAC MMC Control Register
DS33Z41 Quad IMUX Ethernet Mapper 130 of 167 Register Name: SU.MMCCTRL Register Description: MAC MMC Control Register Register Address: 0100h (indirect) 0100h: Bit # 31 30 29 28 27 26 25 24 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default 0 0 0 0 0 0 0 0 0101h: Bi...
Page 133 - MAC All Frames Received Counter
DS33Z41 Quad IMUX Ethernet Mapper 133 of 167 Register Name: SU.RxFrmCtr Register Description: MAC All Frames Received Counter Register Address: 0200h (indirect) 0200h: Bit # 31 30 29 28 27 26 25 24 Name RXFRMC31 RXFRMC30 RXFRMC29 RXFRMC28 RXFRMC27 RXFRMC26 RXFRMC25 RXFRMC24 Default 0 0 0 0 0 0 0 0 0...
Page 134 - MAC Frames Received OK Counter
DS33Z41 Quad IMUX Ethernet Mapper 134 of 167 Register Name: SU.RxFrmOkCtr Register Description: MAC Frames Received OK Counter Register Address: 0204h (indirect) 0204h: Bit # 31 30 29 28 27 26 25 24 Name RXFRMOK31 RXFRMOK30 RXFRMOK29 RXFRMOK28 RXFRMOK27 RXFRMOK26 RXFRMOK25 RXFRMOK24 Default 0 0 0 0 ...
Page 135 - MAC All Frames Transmitted Counter
DS33Z41 Quad IMUX Ethernet Mapper 135 of 167 Register Name: SU.TxFrmCtr Register Description: MAC All Frames Transmitted Counter Register Address: 0300h (indirect) 0300h: Bit # 31 30 29 28 27 26 25 24 Name TXFRMC31 TXFRMC30 TXFRMC29 TXFRMC28 TXFRMC27 TXFRMC26 TXFRMC25 TXFRMC24 Default 0 0 0 0 0 0 0 ...
Page 136 - MAC All Bytes Transmitted Counter
DS33Z41 Quad IMUX Ethernet Mapper 136 of 167 Register Name: SU.TxBytesCtr Register Description: MAC All Bytes Transmitted Counter Register Address: 0308h (indirect) 0308h: Bit # 31 30 29 28 27 26 25 24 Name TXBYTEC31 TXBYTEC30 TXBYTEC29 TXBYTEC28 TXBYTEC27 TXBYTEC26 TXBYTEC25 TXBYTEC24 Default 0 0 0...
Page 137 - MAC Bytes Transmitted OK Counter
DS33Z41 Quad IMUX Ethernet Mapper 137 of 167 Register Name: SU.TxBytesOkCtr Register Description: MAC Bytes Transmitted OK Counter Register Address: 030Ch (indirect) 030Ch: Bit # 31 30 29 28 27 26 25 24 Name TXBYTEOK31 TXBYTEOK30 TXBYTEOK29 TXBYTEOK28 TXBYTEOK27 TXBYTEOK26 TXBYTEOK25 TXBYTEOK24 Defa...
Page 138 - MAC Transmit Frame Under Run Counter
DS33Z41 Quad IMUX Ethernet Mapper 138 of 167 Register Name: SU.TXFRMUNDR Register Description: MAC Transmit Frame Under Run Counter Register Address: 0334h (indirect) 0334h: Bit # 31 30 29 28 27 26 25 24 Name TXFRMU31 TXFRMU30 TXFRMU29 TXFRMU28 TXFRMU27 TXFRMU26 TXFRMU25 TXFRMU24 Default 0 0 0 0 0 0...
Page 139 - MAC All Frames Aborted Counter
DS33Z41 Quad IMUX Ethernet Mapper 139 of 167 Register Name: SU.TxBdFrmCtr Register Description: MAC All Frames Aborted Counter Register Address: 0338h (indirect) 0338h: Bit # 31 30 29 28 27 26 25 24 Name TXFRMBD31 TXFRMBD30 TXFRMBD29 TXFRMBD28 TXFRMBD27 TXFRMBD26 TXFRMBD25 TXFRMBD24 Default 0 0 0 0 ...
Page 140 - 0 FUNCTIONAL TIMING; MII and RMII Interfaces
DS33Z41 Quad IMUX Ethernet Mapper 140 of 167 10 FUNCTIONAL TIMING 10.1 MII and RMII Interfaces Each MII Interface Transmit Port has its own TX_CLK and data interface. The data TXD [3:0] operates synchronously with TX_CLK. The LSB is presented first. TX_CLK should be 2.5MHz for 10Mbps operation and 2...
Page 141 - Figure 10-3. MII Receive Functional Timing; Figure 10-5 RMII Receive Interface Functional Timing
DS33Z41 Quad IMUX Ethernet Mapper 141 of 167 Receive Data (RXD[3:0]) is clocked from the external PHY synchronously with RX_CLK. The RX_CLK signal is 2.5MHz for 10Mbps operation and 25MHz for 100Mbps operation. RX_DV is asserted by the PHY from the first Nibble of the preamble in 100Mbps operation o...
Page 142 - 1 OPERATING PARAMETERS; ABSOLUTE MAXIMUM RATINGS
DS33Z41 Quad IMUX Ethernet Mapper 142 of 167 11 OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Lead with Respect to V SS (except V DD )………………………………………….–0.5V to +5.5V Supply Voltage (VDD3.3) Range with Respect to V SS .……………………………………………………–0.3V to +3.6V Supply Voltage (VDD1.8) Ra...
Page 143 - Thermal Characteristics; PARAMETER MIN; Ambient Temperature; AIR FLOW
DS33Z41 Quad IMUX Ethernet Mapper 143 of 167 Note 1: Typical power is 145mW. Note 2: All outputs loaded with rated capacitance; all inputs between VDD and VSS; inputs with pullups connected to V DD . Note 3: RST pin held low, or RST bit set. Note 4: RST pin held low, or RST bit set. All clocks stopp...
Page 144 - PARAMETER SYMBOL; ns
DS33Z41 Quad IMUX Ethernet Mapper 144 of 167 11.2 MII Interface Table 11-5. Transmit MII Interface 10Mbps 100Mbps PARAMETER SYMBOL MIN TYP MAX MIN TYP MAX UNITS TX_CLK Period t1 400 40 ns TX_CLK Low Time t2 140 260 14 26 ns TX_CLK High Time t3 140 260 14 26 ns TX_CLK to TXD, TX_EN Delay t4 0 20 0 20...
Page 145 - Period; Figure 11-2. Receive MII Interface Timing
DS33Z41 Quad IMUX Ethernet Mapper 145 of 167 Table 11-6. Receive MII Interface 10Mbps 100Mbps PARAMETER SYMBOL MIN TYP MAX MIN TYP MAX UNITS RX_CLK Period t5 400 40 ns RX_CLK Low Time t6 140 260 14 26 ns RX_CLK High Time t7 140 260 14 26 ns RXD, RX_DV to RX_CLK Setup Time t8 5 5 ns RX_CLK to RXD, RX...
Page 147 - MHz; Figure 11-4. Receive RMII Interface Timing
DS33Z41 Quad IMUX Ethernet Mapper 147 of 167 Table 11-8. Receive RMII Interface 10Mbps 100Mbps PARAMETER SYMBOL MIN TYP MAX MIN TYP MAX UNITS REF_CLK Frequence 50MHz ± 50ppm 50MHz ± 50ppm MHz REF_CLK Period t1 20 20 ns REF_CLK Low Time t2 7 13 7 13 ns REF_CLK High Time t3 7 13 7 13 ns RXD, CRS_DV to...
Page 148 - MDC
DS33Z41 Quad IMUX Ethernet Mapper 148 of 167 11.4 MDIO Interface Table 11-9. MDIO Interface PARAMETER SYMBOL MIN TYP MAX UNITS MDC Frequency 1.67 MHz MDC Period t1 540 600 660 ns MDC Low Time t2 270 300 330 ns MDC High Time t3 270 300 330 ns MDC to MDIO Output Delay t4 20 10 ns MDIO Setup Time t5 10...
Page 149 - Transmit WAN Interface; TCLKI
DS33Z41 Quad IMUX Ethernet Mapper 149 of 167 11.5 Transmit WAN Interface Table 11-10. Transmit WAN Interface PARAMETER SYMBOL MIN TYP MAX UNITS TCLKI Frequency 52 MHz TCLKI Period t1 19.2 ns TCLKI Low Time t2 8 ns TCLKI High Time t3 8 ns TCLKI to TSER Output Delay t4 3 10 ns TSYNC Setup Time t5 3.5 ...
Page 150 - Receive WAN Interface; RCLKI
DS33Z41 Quad IMUX Ethernet Mapper 150 of 167 11.6 Receive WAN Interface Table 11-11. Receive WAN Interface PARAMETER SYMBOL MIN TYP MAX UNITS RCLKI Frequency 52 MHz RCLKI Period t1 19.2 ns RCLKI Low Time t2 8 ns RCLKI High Time t3 8 ns RSER Setup Time t4 7 ns RSYNC Setup Time t4 7 ns RSER Hold Time ...
Page 153 - Figure 11-9. Receive IBO Channel Interleave Mode Timing
DS33Z41 Quad IMUX Ethernet Mapper 153 of 167 Figure 11-9. Receive IBO Channel Interleave Mode Timing Note 1: 8.192MHz bus configuration. Note 2: Data on unused channels must be filled with all ones. RSER LSB RCLKI RSYNC LINK 4, CHANNEL 32 MSB LSB LINK 1, CHANNEL 1 MSB LSB LINK 2, CHANNEL 1 RSYNC RSE...
Page 154 - Figure 11-10. Transmit IBO Channel Interleave Mode Timing; Unused channels filled with FFh.
DS33Z41 Quad IMUX Ethernet Mapper 154 of 167 Figure 11-10. Transmit IBO Channel Interleave Mode Timing Note 1: 8.192MHz bus configuration. Note 2: Unused channels filled with FFh.
Page 158 - JTAG Interface Timing; Figure 11-15. JTAG Interface Timing Diagram
DS33Z41 Quad IMUX Ethernet Mapper 158 of 167 11.9 JTAG Interface Timing Table 11-14. JTAG Interface Timing (VDD3.3 = 3.3V ± 5%, VDD1.8 = 1.8V ± 5%, Tj = -40 ° C to +85 ° C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS JTCLK Clock Period t1 1000 ns JTCLK Clock High:Low Time t2:t3 (Note 1) 50 500 ns...
Page 159 - 2 JTAG INFORMATION; Figure 12-1. JTAG Functional Block Diagram
DS33Z41 Quad IMUX Ethernet Mapper 159 of 167 12 JTAG INFORMATION The device supports the standard instruction codes SAMPLE:PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. The device contains the following as required by IEEE 1149.1 Standard Test Acces...
Page 160 - JTAG TAP Controller State Machine Description; TAP Controller State Machine; for a diagram of the state machine operation.
DS33Z41 Quad IMUX Ethernet Mapper 160 of 167 12.1 JTAG TAP Controller State Machine Description This section covers the details on the operation of the Test Access Port (TAP) Controller State Machine. The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising...
Page 164 - DEVICE
DS33Z41 Quad IMUX Ethernet Mapper 164 of 167 12.3 JTAG ID Codes Table 12-2. ID Code Structure DEVICE REVISION ID[31:28] DEVICE CODE ID[27:12] MANUFACTURER’S CODE ID[11:1] REQUIRED ID[0] DS33Z41 0000 0000 0000 0110 0010 000 1010 0001 1 12.4 Test Registers IEEE 1149.1 requires a minimum of two test re...
Page 165 - JTAG Functional Timing; This functional timing for the JTAG circuits shows:
DS33Z41 Quad IMUX Ethernet Mapper 165 of 167 12.5 JTAG Functional Timing This functional timing for the JTAG circuits shows: • The JTAG controller starting from reset state. • Shifting out the first 4 LSB bits of the IDCODE. • Shifting in the BYPASS instruction (111) while shifting out the mandatory...
Page 166 - 3 PACKAGE INFORMATION
DS33Z41 Quad IMUX Ethernet Mapper 166 of 167 13 PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. The package number provided for each package is a link to the latest package outline information.) 13.1 169-Ball CSBGA, 14mm x 14mm ( 56-G60...
Page 167 - 4 DOCUMENT REVISION HISTORY; REVISION DESCRIPTION; Product
DS33Z41 Quad IMUX Ethernet Mapper 167 of 167 Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to chang...
