Page 2 - SECLK
MAX12557 Dual, 65Msps, 14-Bit, IF/Baseband ADC 2 _______________________________________________________________________________________ ABSOLUTE MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS (V DD = 3.3V, OV DD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), C L ≈ 10pF at digital outputs, V IN =...
Page 7 - Typical Operating Characteristics; pF at digital outputs, V
MAX12557 Dual, 65Msps, 14-Bit, IF/Baseband ADC _______________________________________________________________________________________ 7 ELECTRICAL CHARACTERISTICS (continued) (V DD = 3.3V, OV DD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), C L ≈ 10pF at digital outputs, V IN = -0.5dBFS (di...
Page 8 - Typical Operating Characteristics (continued)
MAX12557 Dual, 65Msps, 14-Bit, IF/Baseband ADC 8 _______________________________________________________________________________________ -2.0 -1.0 -1.5 0 -0.5 0.5 1.0 1.5 2.0 0 4096 6144 2048 8192 10240 12288 14336 16384 INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE (4,194,304-POINT DATA RECORD) MAX...
Page 10 - vs. DIGITAL SUPPLY VOLTAGE
MAX12557 Dual, 65Msps, 14-Bit, IF/Baseband ADC 10 ______________________________________________________________________________________ 60 65 75 70 80 85 3.0 3.2 3.1 3.3 3.4 3.5 3.6 -THD, SFDR vs. ANALOG SUPPLY VOLTAGE (f CLK = 65.00352MHz, f IN = 175MHz) MAX12557 toc22 V DD (V) -THD, SFDR (dBc) SF...
Page 11 - GAIN ERROR vs. TEMPERATURE
MAX12557 Dual, 65Msps, 14-Bit, IF/Baseband ADC ______________________________________________________________________________________ 11 60 66 64 62 72 70 68 74 76 -40 10 -15 35 60 85 SNR, SINAD vs. TEMPERATURE(f IN = 175MHz, A IN = -0.5dBFS) MAX12557 toc31 TEMPERATURE ( ° C) SNR, SINAD (dB) SNR SIN...
Page 12 - Pin Description
MAX12557 Dual, 65Msps, 14-Bit, IF/Baseband ADC 12 ______________________________________________________________________________________ PIN NAME FUNCTION 1, 4, 5, 9, 13, 14, 17 GND Converter Ground. Connect all ground pins and the exposed paddle (EP) together. 2 INAP Channel A Positive Analog Input...
Page 14 - Detailed Description; PIN; Figure 1. Pipeline Architecture—Stage Blocks
MAX12557 Detailed Description T h e M A X 1 2 5 5 7 u s e s a 1 0 - s t a g e , f u l l y d i f f e r e n t i a l ,pipelined architecture (Figure 1) that allows for high-speed conversion while minimizing power consump-tion. Samples taken at the inputs move progressivelythrough the pipeline stages ev...
Page 15 - Figure 2. Functional Diagram
MAX12557 Dual, 65Msps, 14-Bit, IF/Baseband ADC ______________________________________________________________________________________ 15 INBP 14-BIT PIPELINE ADC DIGITAL ERROR CORRECTION CHANNEL AREFERENCE SYSTEM COMA REFAN REFAP OV DD DAV OUTPUT DRIVERS DORA CLOCK DIVIDER DATA FORMAT 14-BIT PIPELIN...
Page 16 - common-mode voltage of V; Reference Output; to GND when the MAX12557 is powered; Reference Configurations; with a V; REFIN; REFERENCE MODE; Table 1. Reference Modes
MAX12557 Analog Inputs and Input Track-and-Hold (T/H) Amplifier Figure 3 displays a simplified functional diagram of theinput T/H circuit. This input T/H circuit allows for highanalog input frequencies of 175MHz and beyond andsupports a V DD / 2 common-mode input voltage. The MAX12557 sampling clock...
Page 17 - Applications Information; Clock Duty-Cycle Equalizer
to GND. Bypass REF_P to REF_N with a 10µF capacitor.Bypass REFIN and REFOUT to GND with a 0.1µF capac-itor. The REFIN input impedance is very large (>50M Ω ). When driving REFIN through a resistive divider, useresistances ≥ 10k Ω to avoid loading REFOUT. Buffered external reference mode is virtua...
Page 18 - System Timing Requirements; Figure 4. Siimplified Clock Input Circuit; FUNCTION; Not Allowed; Figure 5. System Timing Diagram
MAX12557 select either one-half or one-fourth of the clock speed fors a m p l i n g p r o v i d e s d e s i g n f l e x i b i l i t y , r e l a x e s c l o c krequirements, and can minimize clock jitter. System Timing Requirements Figure 5 shows the timing relationship between theclock, analog input...
Page 19 - Digital Output Data and Output Format Selection
externally isolates it from heavy capacitive loads. Referto the MAX12557 EV kit schematic for recommendationsof how to drive the DAV signal through an external buffer. Data Out-of-Range Indicator The DORA and DORB digital outputs indicate when theanalog input voltage is out of range. When DOR_ is hi...
Page 22 - Using Transformer Coupling; termination resistors provide an equivalent
MAX12557 Applications Information Using Transformer Coupling In general, the MAX12557 provides better SFDR andTHD with fully differential input signals than single-ended input drive, especially for input frequenciesabove 125MHz. In differential input mode, even-orderharmonics are lower as both input...
Page 24 - Board Layout; Figure 13. External Unbuffered Reference Driving Multiple ADCs
MAX12557 ence, allowing REF_P, REF_N, and COM_ to be drivendirectly by a set of external reference sources. Figure 13 uses a MAX6029 precision 3.000V bandgapreference as a common reference for multiple convert-ers. A seven-component resistive divider chain followsthe MAX6029 voltage reference. The 0...
Page 25 - mount devices for minimum inductance. Bypass V; to; to GND with a 220μF ceramic; Parameter Definitions; Electrical Characteristics; Offset Error; RMS
mount devices for minimum inductance. Bypass V DD to GND with a 220µF ceramic capacitor in parallel with atleast one 10µF, one 4.7µF, and one 0.1µF ceramiccapacitor. Bypass OV DD to GND with a 220µF ceramic capacitor in parallel with at least one 10µF, one 4.7µF,a n d o n e 0 . 1 µ F c e ra mi c c a...
Page 26 - Aperture Jitter; AJ; Aperture Delay; OUT; Overdrive Recovery Time; THD
MAX12557 Total Harmonic Distortion (THD) THD is the ratio of the RMS sum of the first six harmon-ics of the input signal to the fundamental itself. This isexpressed as: where V 1 is the fundamental amplitude, and V 2 through V 7 are the amplitudes of the 2nd- through 7th-order harmonics (HD2 through...
Page 27 - THIN QFN; Pin Configuration
Gain Matching Gain matching is a figure of merit that indicates howwell the gains between the two channels are matchedto each other. The same input signal is applied to bothchannels and the maximum deviation in gain is report-ed (typically in dB) as gain matching. Offset Matching Like gain matching,...
Page 28 - Package Information
MAX12557 Dual, 65Msps, 14-Bit, IF/Baseband ADC Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses areimplied. Maxim reserves the right to change the circuitry and specifications without notice at any time....