Page 2 - DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver; TABLE OF CONTENTS; HDLC E
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 2 of 344 TABLE OF CONTENTS 1 DESCRIPTION ................................................................................................................................... 9 2 FEATURE HIGHLIGHTS ..............................................
Page 3 - BERT
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 3 of 344 9.14.1 DTE and DCE Mode .............................................................................................................................58 9.15 E THERNET MAC ..............................................................
Page 4 - FDL S
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 4 of 344 10.17.4 FIFO Information ...................................................................................................................................96 10.17.5 Receive Packet-Bytes Available ...................................
Page 6 - LIST OF FIGURES
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 6 of 344 LIST OF FIGURES Figure 3-1. Ethernet-to-WAN Extension (With or Without Framing) ......................................................................... 17 Figure 6-1. Main Block Diagram .............................................
Page 8 - LIST OF TABLES; CST
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 8 of 344 LIST OF TABLES Table 2-1. T1-Related Telecommunications Specifications ...................................................................................... 16 Table 7-1. Detailed Pin Descriptions ...................................
Page 9 - DESCRIPTION; coax
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 9 of 344 1 DESCRIPTION The DS33R11 provides interconnection and mapping functionality between Ethernet Packet Systems and T1/E1/J1 WAN Time-Division Multiplexed (TDM) systems. The device is composed of a 10/100 Ethernet MAC, Packet Arbiter...
Page 11 - Microprocessor Interface
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 11 of 344 2 FEATURE HIGHLIGHTS 2.1 General • 256-pin, 27mm BGA package • 1.8V and 3.3V supplies • IEEE 1149.1 JTAG boundary scan • Software access to device ID and silicon revision • Development support includes evaluation kit, driver sour...
Page 15 - Test and Diagnostics
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 15 of 344 2.14 Test and Diagnostics • IEEE 1149.1 support • Programmable on-chip bit error-rate tester (BERT) • Pseudorandom patterns including QRSS • User-defined repetitive patterns • Daly pattern • Error insertion single and continuous ...
Page 16 - Specifications Compliance; X.86—Ethernet over LAPS
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 16 of 344 2.15 Specifications Compliance The DS33R11 meets relevant telecommunications specifications. The following table provides the specifications and relevant sections that are applicable to the DS33R11. Table 2-1. T1-Related Telecomm...
Page 17 - APPLICATIONS; Unframed T1/E1 WAN Bridge
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 17 of 344 3 APPLICATIONS The DS33R11 is ideal for application areas such as transparent LAN service, LAN extension, and Ethernet delivery over T1/E1/J1, T3/E3, OC-1/EC-1, G.SHDSL, or HDSL2/4. For an example of a complete LAN-to-WAN design,...
Page 18 - ACRONYMS AND GLOSSARY
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 18 of 344 4 ACRONYMS AND GLOSSARY • BERT: Bit Error-Rate Tester • DCE: Data Communication Interface • DTE: Data Terminating Interface • FCS: Frame Check Sequence • HDLC: High-Level Data Link Control • MAC: Media Access Control • MII: Media...
Page 19 - MAJOR OPERATING MODES
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 19 of 344 5 MAJOR OPERATING MODES Microprocessor control is possible through the 8-bit parallel control port and provides configuration for all the features of the device. The Ethernet Link Transport Engine in the device can be configured ...
Page 20 - BLOCK DIAGRAMS; AG Pin; ETHERNET
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 20 of 344 6 BLOCK DIAGRAMS Figure 6-1. Main Block Diagram TTIP TRING RTIP RRING SYSCLKI (RMII MODE) RXD[0:1] RX_CLK CRS_DV RX_ERR REF_CLK REF_CLKO TX_EN TXD[0:1] MDC MDIO MCLK TDCLKI TDCLKO TPOSI TPOSO TNEGI TNEGO TCHBLK TCHCLK TCLKT TSERI...
Page 21 - HOST INTERFACE; NET; CLOCK; BACK; LIU
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 21 of 344 Figure 6-2. Block Diagram of T1/E1/J1 Transceiver TX LIU CLOCK ADAPTER BACKPLANE INTERFACE CIRCUIT HOST INTERFACE T1 /E 1 /J 1 NET W O RK CLOCK JTAG ESIB RX LIU JI TTER ATTEN U A T O R LO CAL L O O PBACK RE M O TE L O O PBACK FRA...
Page 25 - PIN DESCRIPTIONS; Pin Functional Description; NAME PIN
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 25 of 344 7 PIN DESCRIPTIONS 7.1 Pin Functional Description Note that all digital pins are IO pins in JTAG mode. This feature increases the effectiveness of board level ATPG patterns. LEGEND: I = input, O = output, Ipu = input with pullup,...
Page 28 - RST; DCE or DTE Selection:
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 28 of 344 NAME PIN TYPE FUNCTION TXD[0] F19 TXD[1] F18 TXD[2] E20 TXD[3] E19 O Transmit Data 0 through 3(MII): TXD [3:0] is presented synchronously with the rising edge of TX_CLK. TXD [0] is the least significant bit of the data. When TX_E...
Page 32 - Channel Blocking Registers
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 32 of 344 NAME PIN TYPE FUNCTION TSIG B4 I Transmit Signaling Input for the T1/E1/J1 Transceiver: When enabled, this input will sample signaling bits for insertion into outgoing PCM data stream. Sampled on the falling edge of TCLKT when th...
Page 41 - FUNCTIONAL
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 41 of 344 8 FUNCTIONAL DESCRIPTION The DS33R11 provides interconnection and mapping functionality between Ethernet packet LANs and T1/E1/J1 WAN Time-Division Multiplexed (TDM) systems. The device is composed of a 10/100 Ethernet MAC, packe...
Page 42 - Interface; AC Electrical Characteristics
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 42 of 344 Both the transmit and receive path of the integrated T1/E1/J1 transceiver also have two HDLC controllers. The HDLC controllers transmit and receive data through the framer block. The HDLC controllers can be assigned to any time s...
Page 43 - ETHERNET MAPPER; Ethernet Mapper Clocks
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 43 of 344 9 ETHERNET MAPPER 9.1 Ethernet Mapper Clocks The DS33R11 clocks sources and functions are as follows: • Serial Transmit Data (TCLKE) and Serial Receive Data (RCLKI) clock inputs are used to transfer data from the serial interface...
Page 46 - Resets and Low Power Modes; RESET FUNCTION
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 46 of 344 9.2 Resets and Low Power Modes The external RST pin and the global reset bit in GL.CR1 create an internal global reset signal. The global reset signal resets the status and control registers on the chip (except the GL.CR1 . RST b...
Page 47 - Initialization and Configuration; EXAMPLE DEVICE INITIALIZATION SEQUENCE:; Global Register Definitions; Resources
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 47 of 344 9.3 Initialization and Configuration EXAMPLE DEVICE INITIALIZATION SEQUENCE: STEP 1: Apply 3.3V supplies, then apply 1.8V supplies. STEP 2: Reset the integrated Ethernet Mapper by pulling the RST pin low or by using the software ...
Page 48 - Interrupts; to initially determine the source of the interrupt.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 48 of 344 9.6 Device Interrupts Figure 9-2 diagrams the flow of interrupt conditions from their source status bits through the multiple levels of information registers and mask bits to the interrupt pin. When an interrupt occurs, the host ...
Page 49 - Figure 9-2. Device Interrupt Information Flow Diagram; Interrupt Pin
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 49 of 344 Figure 9-2. Device Interrupt Information Flow Diagram Receive FCS Errored Packet 7 Receive Aborted Packet 6 Receive Invalid Packet Detected 5 Receive Small Packet Detected 4 Receive Large Packet Detected 3 Receive FCS Errored Pac...
Page 50 - Interrupt Information Registers
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 50 of 344 9.7 Interrupt Information Registers The interrupt information registers provide an indication of which status registers (SR1 through SR9) are generating an interrupt. When an interrupt occurs, the host can read TR.IIR1 and TR.IIR...
Page 51 - Connections and Queues; size
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 51 of 344 9.11 Connections and Queues The multi-port devices in this product family provide bidirectional cross-connections between the multiple Ethernet ports and Serial ports when operating in software mode. A single connection is preser...
Page 52 - Table 9-3. Registers Related to Connections and Queues; REGISTER FUNCTION
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 52 of 344 It is recommended that the user reset the queue pointers for the connection after disconnection. The pointers must be reset before a connection is made. If this disconnect/connect procedure is not followed, incorrect data may be ...
Page 55 - Figure 9-3. Flow Control Using Pause Control Frame; bit is set. If the queue remains above the high threshold,
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 55 of 344 Figure 9-3. Flow Control Using Pause Control Frame Receive Queue Growth Receive Queue High Water Mark Initiate Flow control 8 Rx Data Receive Queue Low Water 9.13.2 Half Duplex Flow Control Half duplex flow control uses a jamming...
Page 56 - Ethernet Interface Port; behavior and should be avoided.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 56 of 344 9.14 Ethernet Interface Port The Ethernet port interface allows for direct connection to an Ethernet PHY. The interface consists of a 10/100Mbit/s MII/RMII interface and an Ethernet MAC. In RMII operation, the interface contains ...
Page 57 - Table 9-5. Registers Related to Setting the Ethernet Port; REGISTER NAME
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 57 of 344 The MAC circuitry generates a frame status for every frame that is received. This real time status can be read by SU.RFSB0 to SU.RFSB3 . Note the frame status is the “real time” status and hence the value will change as new frame...
Page 58 - DCE
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 58 of 344 9.14.1 DTE and DCE Mode The Ethernet MII/RMII port can be configured for DCE or DTE Mode. When the port is configured for the DTE Mode it can be connected to an Ethernet PHY. In DCE mode, the port can be connected to MII/RMII MAC...
Page 59 - Figure 9-6. DS33R11 Configured as a DCE in MII Mode
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 59 of 344 Figure 9-6. DS33R11 Configured as a DCE in MII Mode MAC TXD[3:0] RXD[3:0] TX_CLK RX_CLK TX_ERR RX_ERR TX_EN RX_CRS COL_DET COL_DET DTE DCE TX_EN RXDV MDC MDIO TXD[3:0] RXD[3:0] TX_CLK DS33Z11 MAC RX_CLK RXDV RX_CRS MDIO MDC Rx Tx...
Page 62 - PHY MII Management Block and MDIO Interface; clock is internally generated and runs at 1.67MHz.; BERT in the Ethernet Mapper; The RDEN and TDEN are inputs that can be used to “gap” bits.; BERT Features; PRBS and QRSS patterns of 2
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 62 of 344 9.15.3 PHY MII Management Block and MDIO Interface The MII Management Block allows for the host to control up to 32 PHYs, each with 32 registers. The MII block communicates with the external PHY using 2-wire serial interface comp...
Page 63 - Figure 9-9. PRBS Synchronization State Diagram; Sync
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 63 of 344 9.16.1 Receive Data Interface 9.16.1.1 Receive Pattern Detection The Receive BERT receives only the payload data and synchronizes the receive pattern generator to the incoming pattern. The receive pattern generator is a 32-bit sh...
Page 64 - Repetitive Pattern Synchronization; Figure 9-10. Repetitive Pattern Synchronization State Diagram
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 64 of 344 9.16.2 Repetitive Pattern Synchronization Repetitive pattern synchronization synchronizes the receive pattern generator to the incoming repetitive pattern. The receive pattern generator is synchronized by searching each incoming ...
Page 65 - Transmit Packet Processor; The packet scrambler is a x
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 65 of 344 9.16.4.1 Error Insertion Error insertion inserts errors into the outgoing pattern data stream. Errors are inserted one at a time Single bit error insertion can be initiated from the microprocessor interface. If pattern inversion ...
Page 66 - Receive Packet Processor; The packet descrambler is a self-synchronous x
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 66 of 344 9.18 Receive Packet Processor The Receive Packet Processor accepts data from the Receive Serial Interface performs packet descrambling, packet delineation, inter-frame fill filtering, packet abort detection, destuffing, packet si...
Page 67 - Figure 9-11. HDLC Encapsulation of MAC Frame
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 67 of 344 Bit reordering changes the bit order of each byte. If bit reordering is disabled, the incoming 8-bit data stream DT[1:8] with DT[1] being the MSB and DT[8] being the LSB is output to the Receive FIFO with the MSB in RFD[7] (or 15...
Page 68 - Figure 9-12. LAPS Encoding of MAC Frames Concept
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 68 of 344 9.19 X.86 Encoding and Decoding X.86 protocol provides a method for encapsulating Ethernet Frame onto LAPS. LAPS provides HDLC type framing structure for encapsulation of Ethernet frames. LAPS encapsulated frames can be used to s...
Page 71 - Committed Information Rate Controller; . The CIR will restrict the data flow from
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 71 of 344 9.20 Committed Information Rate Controller The DS33R11 provides a CIR provisioning facility. The CIR can be used restricts the transport of received MAC data to a programmable rate. The CIR location is shown in the Figure 6-1 . T...
Page 73 - TRANSMIT CLOCK SOURCE
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 73 of 344 Table 10-1. T1/E1/J1 Transmit Clock Source TCSS1 TCSS0 TRANSMIT CLOCK SOURCE 0 0 The TCLKT pin (C) is always the source of transmit clock. 0 1 Switch to the recovered clock (B) when the signal at the TCLKT pin fails to transition...
Page 74 - T1 Framer/Formatter Control and Status
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 74 of 344 10.4 T1 Framer/Formatter Control and Status The T1 framer portion of the transceiver is configured through a set of nine control registers. Typically, the control registers are only accessed when the system is first powered up. O...
Page 76 - E1 Framer/Formatter Control and Status; FRAME OR; FAS
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 76 of 344 10.5 E1 Framer/Formatter Control and Status The E1 framer portion of the transceiver is configured by a set of four control registers. Typically, the control registers are only accessed when the system is first powered up. Once t...
Page 78 - COUNT EXCESSIVE
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 78 of 344 10.7 Error Counters The transceiver contains four counters that are used to accumulate line-coding errors, path errors, and synchronization errors. Counter update options include one-second boundaries, 42ms (T1 mode only), 62ms (...
Page 79 - Table 10-7. T1 Path Code Violation Counting Arrangements; FRAMING MODE
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 79 of 344 10.7.2 Path Code Violation Count Register (TR.PCVCR) In T1 mode, the path code violation count register records Ft, Fs, or CRC6 errors in T1 frames. When the receive side of a framer is set to operate in the T1 ESF framing mode, ...
Page 81 - DS0 Monitoring Function
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 81 of 344 10.8 DS0 Monitoring Function The transceiver has the ability to monitor one DS0 64kbps channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit direction, the user determine...
Page 82 - Signaling Operation
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 82 of 344 10.9 Signaling Operation There are two methods to access receive signaling data and provide transmit signaling data, processor-based (software-based) or hardware-based. Processor-based refers to access through the transmit and re...
Page 84 - Figure 10-3. Simplified Diagram of Transmit Signaling Path
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 84 of 344 Figure 10-3. Simplified Diagram of Transmit Signaling Path TRANSMIT SIGNALING REGISTERS SIGNALING BUFFERS PER-CHANNEL CONTROL TSER TSIG T1/E1 DATA STREAM PER-CHANNEL CONTROL TR.SSIE1 - TR.SSIE4 B7 TR.T1TCR1.4 1 0 0 1 0 1 TR.PCPR....
Page 85 - TS
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 85 of 344 10.9.3.2 E1 Mode In E1 mode, TS16 carries the signaling information. This information can be in either CCS (common channel signaling) or CAS (channel associated signaling) format. The 32 time slots are referenced by two different...
Page 87 - Example 1; Sets transmit channel 3 idle code to 7Eh; Example 2; Example 3; Sets all transmit idle codes to 7Eh.; Example 5
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 87 of 344 10.10.1 Idle-Code Programming Examples Example 1 Sets transmit channel 3 idle code to 7Eh . Write TR.IAAR = 02h ;select channel 3 in the array Write TR.PCICR = 7Eh ;set idle code to 7Eh Example 2 Sets transmit channels 3, 4, 5, a...
Page 88 - Channel Blocking Registers
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 88 of 344 10.11 Channel Blocking Registers The receive channel blocking registers (TR.RCBR1/TR.RCBR2/TR.RCBR3/TR.RCBR4) and the transmit channel blocking registers (TR.TCBR1/TR.TCBR2/TR.TCBR3/TR.TCBR4) control RCHBLK and TCHBLK pins, respe...
Page 89 - Table 10-11. Elastic Store Delay After Initialization; INITIALIZATION REGISTER
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 89 of 344 10.12.2 Transmit Elastic Store See the TR.IOCR1 and TR.IOCR2 registers for information about clock and I/O configurations. The operation of the transmit elastic store is very similar to the receive side. If the transmit-side elas...
Page 92 - Method 2: Internal Register Scheme Based on CRC4 Multiframe
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 92 of 344 10.15 Additional (Sa) and International (Si) Bit Operation (E1 Only) When operated in the E1 mode, the transceiver provides two methods for accessing the Sa and the Si bits. The first method involves using the internal TR.RAF/TR....
Page 95 - Control; INT; REGISTER CHANNELS
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 95 of 344 10.16.2 FIFO Control The FIFO control register (TR.HxFC) controls and sets the watermarks for the transmit and receive FIFOs. Bits 3, 4, and 5 set the transmit low watermark and the lower 3 bits set the receive high watermark. Wh...
Page 96 - Information
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 96 of 344 10.16.4 FIFO Information The transmit FIFO buffer-available register indicates the number of bytes that can be written into the transmit FIFO. The count form this register informs the host as to how many bytes can be written into...
Page 97 - Section; for
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 97 of 344 10.17 Legacy FDL Support (T1 Mode) 10.17.1 Overview To provide backward compatibility to the older DS21x52 T1 device, the transceiver maintains the circuitry that existed in the previous generation of the T1 framer. In new applic...
Page 99 - Programmable In-Band Loop Code Generation and Detection; This function is available only in T1 mode.; To transmit a pattern, the user loads the pattern into the
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 99 of 344 10.19 Programmable In-Band Loop Code Generation and Detection The transceiver has the ability to generate and detect a repeating bit pattern from one to eight bits or 16 bits in length. This function is available only in T1 mode....
Page 101 - Figure 10-5. Typical Monitor Application; Rt
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 101 of 344 10.20.2.1 Receive Level Indicator and Threshold Interrupt The device reports the signal strength at RTIP and RRING in 2.5dB increments through RL3–RL0 located in Information Register 2 (TR.INFO2). This feature is helpful when tr...
Page 104 - Recommended Circuits; Application Note 324: T1/E1 Network Interface Design; Table 10-13. Transformer Specifications; SPECIFICATION RECOMMENDED
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 104 of 344 10.24 Recommended Circuits Figure 10-7. Basic Interface Refer to Application Note 324: T1/E1 Network Interface Design for more information on protected interfaces. TTIP TRING RTIP RRING DVDD TVDD RVDD VDD DVSS TVSS RVSS DS33R11 ...
Page 106 - DEVICE
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 106 of 344 Figure 10-10. Jitter Tolerance FREQUENCY (Hz) UNIT INTERVALS (UI P- P ) 1k 100 10 1 0.1 10 100 1k 10k 100k DEVICE TOLERANCE 1 TR 62411 (DEC. 90) ITU-T G.823 Figure 10-11. Jitter Tolerance (E1 Mode) FREQUENCY (Hz) UNIT INTERVALS ...
Page 107 - T1 MODE; E1 MODE
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 107 of 344 Figure 10-12. Jitter Attenuation (T1 Mode) FREQUENCY (Hz) 0dB -20dB -40dB -60dB 1 10 100 1K 10K JITTER A TT ENUATION (d B) 100K TR 62411 (Dec. 90) Prohibited Area C urv e B Cu rve A T1 MODE Figure 10-13. Jitter Attenuation (E1 M...
Page 108 - Figure 10-14. Optional Crystal Connections
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 108 of 344 Figure 10-14. Optional Crystal Connections XTALD C1 C2 1.544MHz/2.048MHz MCLK NOTE: C1 AND C2 SHOULD BE 5pF LOWER THAN TWO TIMES THE NOMINAL LOADING CAPACITANCE OF THE CRYSTAL TO ADJUST FOR THE INPUT CAPACITANCE OF THE DEVICE. 1...
Page 112 - Programmable Backplane Clock Synthesizer; for details about programming the per-channel function.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 112 of 344 10.27 Programmable Backplane Clock Synthesizer The transceiver contains an on-chip clock synthesizer that generates a user-selectable clock output on the BPCLK pin, referenced to the recovered receive clock (RCLKO). The synthesi...
Page 113 - T1 TRANSMIT
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 113 of 344 10.29 T1/E1/J1 Transmit Flow Diagrams Figure 10-17. T1/J1 Transmit Flow Diagram ESCR.4 TESE TSER TSIG HSIE1-3 through PCPR TX ESTORE Off-ChipConnection RDATA From T1_rcv_logic LBCR1.1 PLB HDLC Engine #1 THMS1 H1TC.4 H1TCS1-3 H1T...
Page 115 - E1 TRANSMIT
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 115 of 344 Figure 10-18. E1 Transmit Flow Diagram TSER TSIG HSIE1-4 through PCPR TX ESTORE ESCR.4 TESE TESO TDATA Off-ChipConnection RDATAFromE1_rcv_logic LBCR1.1 PLB HDLC Engine #1 THMS1 H1TC.4 H1TCS1-4 H1TTSBS T1SaBE4- T1SaBE8 THMS1 H1TC...
Page 116 - coding Mux; coding Mux
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 116 of 344 Per-Channel Loopback From Idle Code Mux RDATAFrom E1_rcv_logic PCLR1-4 Sa-bit Mux TNAF THMS1 THMS2 H1TC.4 H2TC.4 TS0 Mux TAF/TNAF(non Sa) Si-bit Mux E1TCR1.4 TSIS Auto...
Page 117 - 1 DEVICE REGISTERS; Ten address lines are used to address the register space.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 117 of 344 11 DEVICE REGISTERS Ten address lines are used to address the register space. Table 11-1 shows the register map for the DS33R11. The addressable range for the device is 0000h to 08FFh. Each Register Section is 64 bytes deep. Glo...
Page 118 - Register Bit Maps; contain the registers of the DS33R11.; Global Ethernet Mapper Register Bit Map; Table 11-2. Global Ethernet Mapper Register Bit Map
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 118 of 344 11.1 Register Bit Maps Table 11-2 , Table 11-3 , Table 11-4 , Table 11-5 , Table 11-6 , and Table 11-7 contain the registers of the DS33R11. Bits that are reserved are noted with a single dash “-“. All registers not listed are r...
Page 120 - Serial Interface Register Bit Map; Table 11-5. Serial Interface Register Bit Map
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 120 of 344 11.1.4 Serial Interface Register Bit Map Table 11-5. Serial Interface Register Bit Map A DDR N AME B IT 7 B IT 6 B IT 5 B IT 4 B IT 3 B IT 2 B IT 1 B IT 0 0C0h LI.TSLCR - - - - - - - TDENPLT 0C1h LI.RSTPD - - - - - - RESET - 0C2...
Page 122 - Ethernet Interface Register Bit Map; Table 11-6. Ethernet Interface Register Bit Map
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 122 of 344 11.1.5 Ethernet Interface Register Bit Map Table 11-6. Ethernet Interface Register Bit Map A DDR N AME B IT 7 B IT 6 B IT 5 B IT 4 B IT 3 B IT 2 B IT 1 B IT 0 140h SU.MACRADL MACRA7 MACRA6 MACRA5 MACRA4 MACRA3 MACRA2 MACRA1 MACR...
Page 123 - Table 11-7. MAC Indirect Register Bit Map
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 123 of 344 11.1.6 MAC Register Bit Map Table 11-7. MAC Indirect Register Bit Map A DDR N AME B IT 7 B IT 6 B IT 5 B IT 4 B IT 3 B IT 2 B IT 1 B IT 0 0000h SU.MACCR 31:24 Reserved Reserved Reserved HDB PS Reserved Reserved Reserved 0001h 23...
Page 134 - Global Register Definitions for Ethernet Mapper; Global ID Low Register
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 134 of 344 11.2 Global Register Definitions for Ethernet Mapper Functions contained in the global registers include: framer reset, LIU reset, device ID, and BERT interrupt status. These registers are preserved to provide code compatibility...
Page 135 - Global Control Register 1; Global BERT Connect Register
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 135 of 344 Register Name: GL.CR1 Register Description: Global Control Register 1 Register Address: 02h Bit # 7 6 5 4 3 2 1 0 Name - - - - - REF_CLKO INTM RST Default 0 0 0 Bit 2: REF_CLKO OFF (REF_CLKO) This bit determines if the REF_CLKO ...
Page 141 - Global SDRAM Mode Register 1
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 141 of 344 Register Name: GL.BISTPF Register Description: BIST Pass-Fail Register Address: 21h Bit # 7 6 5 4 3 2 1 0 Name - - - - - - BISTDN BISTPF Default 0 0 0 0 0 0 0 0 Bit 1: BIST DONE (BISTDN) If this bit is set to 1, the DS33R11 has ...
Page 143 - Arbiter Registers; Arbiter Register Bit Descriptions; Arbiter Receive Queue Size Connection; These 7 bits of the size of receive queue associated with the; Queue size of 0 is not allowed and should never be set.; Register Description:; Arbiter Transmit Queue Size Connection 1; This is size of transmit queue associated with the connection. The; Note that queue size of 0 is not allowed and should never be set.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 143 of 344 11.3 Arbiter Registers The Arbiter manages the transport between the Ethernet port and the Serial Interface. It is responsible for queuing and dequeuing data to an external SDRAM. The arbiter handles requests from the HDLC and M...
Page 151 - Serial Interface Registers; Serial Interface Transmit and Common Registers; Serial Interface Transmit Register Bit Descriptions
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 151 of 344 11.5 Serial Interface Registers The Serial Interface contains the Serial HDLC transport circuitry and the associated serial port. The Serial Interface register map consists of registers that are common functions, transmit functi...
Page 153 - Transmit Inter-Frame Gapping Control Register; – These eight bits indicate the number of additional flags; Transmit Errored Packet Low Control Register; – These eight bits indicate the total number
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 153 of 344 Register Name: LI.TIFGC Register Description: Transmit Inter-Frame Gapping Control Register Register Address: 0C5h Bit # 7 6 5 4 3 2 1 0 Name TIFG7 TIFG6 TIFG5 TIFG4 TIFG3 TIFG2 TIFG1 TIFG0 Default 0 0 0 0 0 0 0 1 Bits 0 - 7: Tr...
Page 163 - Receive Packet Processor Status Register Latched
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 163 of 344 Register Name: LI.RPPSRL Register Description: Receive Packet Processor Status Register Latched Register Address: 105h Bit # 7 6 5 4 3 2 1 0 Name REPL RAPL RIPDL RSPDL RLPDL REPCL RAPCL RSPCL Default - - - - - - - - Bit 7: Recei...
Page 174 - Ethernet Interface Registers; Ethernet Interface Register Bit Descriptions; MAC Read Address Low Register
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 174 of 344 11.6 Ethernet Interface Registers The Ethernet Interface registers are used to configure RMII/MII bus operation and establish the MAC parameters as required by the user. The MAC Registers cannot be addressed directly from the Pr...
Page 177 - MAC Address Write High; MAC Read Write Command Status
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 177 of 344 Register Name: SU.MACAWH Register Description: MAC Address Write High Register Address: 14Bh Bit # 7 6 5 4 3 2 1 0 Name MACAW 15 MACAW 14 MACAW 13 MACAW12 MACAW11 MACAW10 MACAW9 MACAW8 Default 0 0 0 0 0 0 0 0 Bits 0 – 7: MAC Wri...
Page 182 - Receive Frame Status Byte 3
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 182 of 344 Register Name: SU.RFSB3 Register Description: Receive Frame Status Byte 3 Register Address: 157h Bit # 7 6 5 4 3 2 1 0 Name MF - - BF MCF UF CF LE Default 0 0 0 0 0 0 0 0 Bit 7: Missed Frame (MF) This bit is set to 1 if the pack...
Page 185 - Receive Frame Rejection Control
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 185 of 344 Register Name: SU.RFRC Register Description: Receive Frame Rejection Control Register Address: 15Eh Bit # 7 6 5 4 3 2 1 0 Name - UCFR CFRR LERR CRCERR DBR MIIER BFR Default 0 0 0 0 0 0 0 0 Bit 6: Uncontrolled Control Frame Rejec...
Page 186 - MAC Control Register
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 186 of 344 11.6.2 MAC Registers The control Registers related to the control of the individual Mac’s are shown in the following Table. The DS33R11 keeps statistics for the packet traffic sent and received. The register address map is shown...
Page 187 - Random Number Generator Bits Used
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 187 of 344 Bit 12: Late Collision Control (LCC) When set to 1, enables retransmission of a collided packet even after the collision period. When this bit is clear, retransmission of late collisions is disabled. Bit 10: Disable Retry (DRTY)...
Page 188 - MAC MII Management (MDIO) Address Register
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 188 of 344 Register Name: SU.MACMIIA Register Description: MAC MII Management (MDIO) Address Register Register Address: 0014h (indirect) 0014h: Bit # 31 30 29 28 27 26 25 24 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserv...
Page 190 - MAC Flow Control Register
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 190 of 344 Register Name: SU.MACFCR Register Description: MAC Flow Control Register Register Address: 001Ch (indirect) 001Ch: Bit # 31 30 29 28 27 26 25 24 Name PT15 PT14 PT13 PT12 PT11 PT10 PT09 PT08 Default 0 0 0 0 0 0 0 0 001Dh: Bit # 2...
Page 191 - MAC MMC Control Register
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 191 of 344 Register Name: SU.MMCCTRL Register Description: MAC MMC Control Register Register Address: 0100h (indirect) 0100h: Bit # 31 30 29 28 27 26 25 24 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Defaul...
Page 194 - MAC All Frames Received Counter
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 194 of 344 Register Name: SU.RxFrmCtr Register Description: MAC All Frames Received Counter Register Address: 0200h (indirect) 0200h: Bit # 31 30 29 28 27 26 25 24 Name RXFRMC31 RXFRMC30 RXFRMC29 RXFRMC28 RXFRMC27 RXFRMC26 RXFRMC25 RXFRMC2...
Page 195 - MAC Frames Received OK Counter
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 195 of 344 Register Name: SU.RxFrmOkCtr Register Description: MAC Frames Received OK Counter Register Address: 0204h (indirect) 0204h: Bit # 31 30 29 28 27 26 25 24 Name RXFRMOK31 RXFRMOK30 RXFRMOK29 RXFRMOK28 RXFRMOK27 RXFRMOK26 RXFRMOK25...
Page 196 - MAC All Frames Transmitted Counter
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 196 of 344 Register Name: SU.TxFrmCtr Register Description: MAC All Frames Transmitted Counter Register Address: 0300h (indirect) 0300h: Bit # 31 30 29 28 27 26 25 24 Name TXFRMC31 TXFRMC30 TXFRMC29 TXFRMC28 TXFRMC27 TXFRMC26 TXFRMC25 TXFR...
Page 197 - MAC All Bytes Transmitted Counter
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 197 of 344 Register Name: SU.TxBytesCtr Register Description: MAC All Bytes Transmitted Counter Register Address: 0308h (indirect) 0308h: Bit # 31 30 29 28 27 26 25 24 Name TXBYTEC31 TXBYTEC30 TXBYTEC29 TXBYTEC28 TXBYTEC27 TXBYTEC26 TXBYTE...
Page 198 - MAC Bytes Transmitted OK Counter
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 198 of 344 Register Name: SU.TxBytesOkCtr Register Description: MAC Bytes Transmitted OK Counter Register Address: 030Ch (indirect) 030Ch: Bit # 31 30 29 28 27 26 25 24 Name TXBYTEOK31 TXBYTEOK30 TXBYTEOK29 TXBYTEOK28 TXBYTEOK27 TXBYTEOK26...
Page 199 - MAC Transmit Frame Under Run Counter
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 199 of 344 Register Name: SU.TxFrmUndr Register Description: MAC Transmit Frame Under Run Counter Register Address: 0334h (indirect) 0334h: Bit # 31 30 29 28 27 26 25 24 Name TXFRMU31 TXFRMU30 TXFRMU29 TXFRMU28 TXFRMU27 TXFRMU26 TXFRMU25 T...
Page 200 - MAC All Frames Aborted Counter
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 200 of 344 Register Name: SU.TxBdFrmCtr Register Description: MAC All Frames Aborted Counter Register Address: 0338h (indirect) 0338h: Bit # 31 30 29 28 27 26 25 24 Name TXFRMBD31 TXFRMBD30 TXFRMBD29 TXFRMBD28 TXFRMBD27 TXFRMBD26 TXFRMBD25...
Page 202 - I/O Configuration Register 1
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 202 of 344 Register Name: TR.IOCR1 Register Description: I/O Configuration Register 1 Register Address: 01h Bit # 7 6 5 4 3 2 1 0 Name RSMS RSMS2 RSMS1 RSIO TSDW TSM TSIO ODF Default 0 0 0 0 0 0 0 0 Bit 7: RSYNC Multiframe Skip Control (RS...
Page 203 - I/O Configuration Register 2
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 203 of 344 Register Name: TR.IOCR2 Register Description: I/O Configuration Register 2 Register Address: 02h Bit # 7 6 5 4 3 2 1 0 Name RCLKINV TCLKINV RSYNCINV TSYNCINV TSSYNCINV H100EN TSCLKM RSCLKM Default 0 0 0 0 0 0 0 0 Bit 7: RCLKO In...
Page 205 - T1 Receive Control Register 2
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 205 of 344 Register Name: TR.T1RCR2 Register Description: T1 Receive Control Register 2 Register Address: 04h Bit # 7 6 5 4 3 2 1 0 Name — RFM RB8ZS RSLC96 RZSE — RJC RD4YM Default 0 0 0 0 0 0 0 0 Bit 6: Receive Frame Mode Select (RFM) 0 =...
Page 206 - T1 Transmit Control Register 1; Name TJC TFPT TCPT TSSE GB7S
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 206 of 344 Register Name: TR.T1TCR1 Register Description: T1 Transmit Control Register 1 Register Address: 05h Bit # 7 6 5 4 3 2 1 0 Name TJC TFPT TCPT TSSE GB7S TFDLS TBL TYEL Default 0 0 0 0 0 0 0 0 Bit 7: Transmit Japanese CRC6 Enable (...
Page 207 - T1 Transmit Control Register 2
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 207 of 344 Register Name: TR.T1TCR2 Register Description: T1 Transmit Control Register 2 Register Address: 06h Bit # 7 6 5 4 3 2 1 0 Name TB8ZS TSLC96 TZSE FBCT2 FBCT1 TD4YM — TB7ZS Default 0 0 0 0 0 0 0 0 Bit 7: Transmit B8ZS Enable (TB8Z...
Page 211 - T1 Receive Digital-Milliwatt Enable Register 1; T1 Receive Digital-Milliwatt Enable Register 2; T1 Receive Digital-Milliwatt Enable Register 3
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 211 of 344 Register Name: TR.T1RDMR1 Register Description: T1 Receive Digital-Milliwatt Enable Register 1 Register Address: 0Ch Bit # 7 6 5 4 3 2 1 0 Name CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 Default 0 0 0 0 0 0 0 0 Bits 0 - 7: Receive Digital-...
Page 215 - Status Register 1
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 215 of 344 Register Name: TR.SR1 Register Description: Status Register 1 Register Address: 16h Bit # 7 6 5 4 3 2 1 0 Name ILUT TIMER RSCOS JALT LRCL TCLE TOCD LOLITC Default 0 0 0 0 0 0 0 0 Bit 7: Input Level Under Threshold (ILUT). This b...
Page 216 - Interrupt Mask Register 1
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 216 of 344 Register Name: TR.IMR1 Register Description: Interrupt Mask Register 1 Register Address: 17h Bit # 7 6 5 4 3 2 1 0 Name ILUT TIMER RSCOS JALT LRCL TCLE TOCD LOLITC Default 0 0 0 0 0 0 0 0 Bit 7: Input Level Under Threshold (ILUT...
Page 217 - Status Register 2
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 217 of 344 Register Name: TR.SR2 Register Description: Status Register 2 Register Address: 18h Bit # 7 6 5 4 3 2 1 0 Name RYELC RUA1C FRCLC RLOSC RYEL RUA1 FRCL RLOS Default 0 0 0 0 0 0 0 0 Bit 7: Receive Yellow Alarm Clear Event (RYELC) (...
Page 218 - Interrupt Mask Register 2
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 218 of 344 Register Name: TR.IMR2 Register Description: Interrupt Mask Register 2 Register Address: 19h Bit # 7 6 5 4 3 2 1 0 Name RYELC RUA1C FRCLC RLOSC RYEL RUA1 FRCL RLOS Default 0 0 0 0 0 0 0 0 Bit 7: Receive Yellow Alarm Clear Event ...
Page 219 - Status Register 3
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 219 of 344 Register Name: TR.SR3 Register Description: Status Register 3 Register Address: 1Ah Bit # 7 6 5 4 3 2 1 0 Name LSPARE LDN LUP LOTC LORC V52LNK RDMA RRA Default 0 0 0 0 0 0 0 0 Bit 7: Spare Code Detected Condition (LSPARE) (T1 On...
Page 220 - Interrupt Mask Register 3; Name LSPARE LDN
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 220 of 344 Register Name: TR.IMR3 Register Description: Interrupt Mask Register 3 Register Address: 1Bh Bit # 7 6 5 4 3 2 1 0 Name LSPARE LDN LUP LOTC LORC V52LNK RDMA RRA Default 0 0 0 0 0 0 0 0 Bit 7: Spare Code Detected Condition (LSPAR...
Page 221 - Status Register 4
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 221 of 344 Register Name: TR.SR4 Register Description: Status Register 4 Register Address: 1Ch Bit # 7 6 5 4 3 2 1 0 Name RAIS-CI RSAO RSAZ TMF TAF RMF RCMF RAF Default 0 0 0 0 0 0 0 0 Bit 7: Receive AIS-CI Event (RAIS-CI) (T1 Only). Set w...
Page 222 - Interrupt Mask Register 4
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 222 of 344 Register Name: TR.IMR4 Register Description: Interrupt Mask Register 4 Register Address: 1Dh Bit # 7 6 5 4 3 2 1 0 Name RAIS-CI RSAO RSAZ TMF TAF RMF RCMF RAF Default 0 0 0 0 0 0 0 0 Bit 7: Receive AIS-CI Event (RAIS-CI) 0 = int...
Page 223 - Status Register 5
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 223 of 344 Register Name: TR.SR5 Register Description: Status Register 5 Register Address: 1Eh Bit # 7 6 5 4 3 2 1 0 Name — — TESF TESEM TSLIP RESF RESEM RSLIP Default 0 0 0 0 0 0 0 0 Bit 5: Transmit Elastic Store Full Event (TESF). Set wh...
Page 224 - Interrupt Mask Register 5
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 224 of 344 Register Name: TR.IMR5 Register Description: Interrupt Mask Register 5 Register Address: 1Fh Bit # 7 6 5 4 3 2 1 0 Name — — TESF TESEM TSLIP RESF RESEM RSLIP Default 0 0 0 0 0 0 0 0 Bit 5: Transmit Elastic Store Full Event (TESF...
Page 229 - Status Register 9
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 229 of 344 Register Name: TR.SR9 Register Description: Status Register 9 Register Address: 26h Bit # 7 6 5 4 3 2 1 0 Name — BBED BBCO BEC0 BRA1 BRA0 BRLOS BSYNC Default 0 0 0 0 0 0 0 0 Bit 6: BERT Bit-Error Detected (BED) Event (BBED). A l...
Page 230 - Interrupt Mask Register 9
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 230 of 344 Register Name: TR.IMR9 Register Description: Interrupt Mask Register 9 Register Address: 27h Bit # 7 6 5 4 3 2 1 0 Name — BBED BBCO BEC0 BRA1 BRA0 BRLOS BSYNC Default 0 0 0 0 0 0 0 0 Bit 6: Bit-Error Detected Event (BBED) 0 = in...
Page 231 - Per-Channel Pointer Register
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 231 of 344 Register Name: TR.PCPR Register Description: Per-Channel Pointer Register Register Address: 28h Bit # 7 6 5 4 3 2 1 0 Name RSAOICS RSRCS RFCS BRCS THSCS PEICS TFCS BTCS Default 0 0 0 0 0 0 0 0 Bit 7: Receive Signaling All-Ones I...
Page 233 - Bits 1 – 5: Unused, must be set to 0 or proper operation
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 233 of 344 Register Name: TR.INFO7 Register Description: Information Register 7 (Real-Time, Non-Latched Register) Register Address: 30h Bit # 7 6 5 4 3 2 1 0 Name CSC5 CSC4 CSC3 CSC2 CSC0 FASSA CASSA CRC4SA Default 0 0 0 0 0 0 0 0 Bits 3 –...
Page 235 - E1 Transmit Control Register 1; Name TFPT T16S TUA1 TSiS TSA1 THDB3
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 235 of 344 Register Name: TR.E1TCR1 Register Description: E1 Transmit Control Register 1 Register Address: 35h Bit # 7 6 5 4 3 2 1 0 Name TFPT T16S TUA1 TSiS TSA1 THDB3 TG802 TCRC4 Default 0 0 0 0 0 0 0 0 Bit 7: Transmit Time Slot 0 Pass-T...
Page 237 - Receive Signaling Change-of-State Information; Receive Signaling Change-of-State Interrupt Enable
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 237 of 344 Register Name: TR.RSINFO1, TR.RSINFO2, TR.RSINFO3, TR.RSINFO4 Register Description: Receive Signaling Change-of-State Information Register Address: 38h, 39h, 3Ah, 3Bh (MSB) (LSB) CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 RSINFO1 CH16 CH15...
Page 238 - Signaling Control Register
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 238 of 344 Register Name: TR.SIGCR Register Description: Signaling Control Register Register Address: 40h Bit # 7 6 5 4 3 2 1 0 Name GRSRE — — RFE RFF RCCS TCCS FRSAO Default 0 0 0 0 0 0 0 0 Bit 7: Global Receive Signaling Reinsertion Enab...
Page 239 - Error-Counter Configuration Register
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 239 of 344 Register Name: TR.ERCNT Register Description: Error-Counter Configuration Register Register Address: 41h Bit # 7 6 5 4 3 2 1 0 Name — MECU ECUS EAMS VCRFS FSBE MOSCRF LCVCRF Default 0 0 0 0 0 0 0 0 Bit 6: Manual Error-Counter Up...
Page 243 - Per-Channel Loopback Enable Register 1; Per-Channel Loopback Enable Register 2; Per-Channel Loopback Enable Register 3; Per-Channel Loopback Enable Register 4
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 243 of 344 Register Name: TR.PCLR1 Register Description: Per-Channel Loopback Enable Register 1 Register Address: 4Bh Bit # 7 6 5 4 3 2 1 0 Name CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 Default 0 0 0 0 0 0 0 0 Bits 0 – 7: Per-Channel Loopback Enabl...
Page 244 - Elastic Store Control Register
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 244 of 344 Register Name: TR.ESCR Register Description: Elastic Store Control Register Register Address: 4Fh Bit # 7 6 5 4 3 2 1 0 Name TESALGN TESR TESMDM TESE RESALGN RESR RESMDM RESE Default 0 0 0 0 0 0 0 0 Bit 7: Transmit Elastic Store...
Page 245 - Transmit Signaling Registers
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 245 of 344 Register Name: TR.TS1 to TR.TS16 Register Description: Transmit Signaling Registers (E1 Mode, CAS Format) Register Address: 50h to 5Fh (MSB) (LSB) 0 0 0 0 X Y X X TS1 CH2-A CH2-B CH2-C CH2-D CH1-A CH1-B CH1-C CH1-D TS2 CH4-A CH4...
Page 250 - Receive Signaling Registers
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 250 of 344 Register Name: TR.RS1 to TR.RS16 Register Description: Receive Signaling Registers (E1 Mode, CAS Format) Register Address: 60h to 6Fh (MSB) (LSB) 0 0 0 0 X Y X X RS1 CH2-A CH2-B CH2-C CH2-D CH1-A CH1-B CH1-C CH1-D RS2 CH4-A CH4-...
Page 257 - Line Interface Control 2
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 257 of 344 Register Name: TR.LIC2 Register Description: Line Interface Control 2 Register Address: 79h Bit # 7 6 5 4 3 2 1 0 Name ETS LIRST IBPV TUA1 JAMUX — SCLD CLDS Default 0 0 0 0 0 0 0 0 Bit 7: E1/T1 Select (ETS) 0 = T1 mode selected ...
Page 263 - Receive Channel Blocking Register 2; Receive Channel Blocking Register 3; Receive Channel Blocking Register 4
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 263 of 344 Register Name: TR.RCBR2 Register Description: Receive Channel Blocking Register 2 Register Address: 89h Bit # 7 6 5 4 3 2 1 0 Name CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 Default 0 0 0 0 0 0 0 0 Bits 0 – 7: Receive Channels 9 to ...
Page 264 - Transmit Channel Blocking Register 1; Transmit Channel Blocking Register 2; Transmit Channel Blocking Register 3; Transmit Channel Blocking Register 4
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 264 of 344 Register Name: TR.TCBR1 Register Description: Transmit Channel Blocking Register 1 Register Address: 8Ch Bit # 7 6 5 4 3 2 1 0 Name CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 Default 0 0 0 0 0 0 0 0 Bits 0 – 7: Transmit Channels 1 to 8 Cha...
Page 266 - TFLWM2 TFLWM1 TFLWM0
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 266 of 344 Register Name: TR.H1FC, TR.H2FC Register Description: HDLC # 1 FIFO Control HDLC # 2 FIFO Control Register Address: 91h, A1h Bit # 7 6 5 4 3 2 1 0 Name — — TFLWM2 TFLWM1 TFLWM0 RFHWM2 RFHWM1 RFHWM0 Default 0 0 0 0 0 0 0 0 Bits 3...
Page 272 - Bits 0 – 7: Transmit FIFO Bytes Available; In-Band Code Control Register; Bit; Bits 6 – 7: Transmit Code Length Definition Bits (TC0 to TC1)
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 272 of 344 Register Name: TR.H1TFBA, TR.H2TFBA Register Description: HDLC # 1 Transmit FIFO Buffer Available HDLC # 2 Transmit FIFO Buffer Available Register Address: 9Fh, Afh Bit # 7 6 5 4 3 2 1 0 Name TFBA7 TFBA6 TFBA5 TFBA4 TFBA3 TFBA2 ...
Page 276 - In-Band Receive Spare Control Register; Bits 3 – 7: Unused, must be set to 0 for proper operation
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 276 of 344 Register Name: TR.RSCC Register Description: In-Band Receive Spare Control Register Register Address: BDh Bit # 7 6 5 4 3 2 1 0 Name — — — — — RSC2 RSC1 RSC0 Default 0 0 0 0 0 0 0 0 Bits 3 – 7: Unused, must be set to 0 for prope...
Page 279 - Transmit FDL Register
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 279 of 344 Register Name: TR.TFDL Register Description: Transmit FDL Register Register Address: C1h Bit # 7 6 5 4 3 2 1 0 Name TFDL7 TFDL6 TFDL5 TFDL4 TFDL3 TFDL2 TFDL1 TFDL0 Default 0 0 0 0 0 0 0 0 Note: Also used to insert Fs framing pat...
Page 300 - 2 FUNCTIONAL TIMING; Figure 12-1. Tx Serial Interface Functional Timing
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 300 of 344 12 FUNCTIONAL TIMING 12.1 Functional Serial I/O Timing The Serial Interface provides flexible timing to interconnect with a wide variety of serial interfaces. TDEN is an input signal that can be used to enable or block the TSERO...
Page 301 - Figure 12-3. Transmit Byte Sync Functional Timing
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 301 of 344 The DS33R11 provides the TBSYNC signal as a byte boundary indication to an external interface when X.86 (LAPS) functionality is selected. The functional timing of TBSYNC is shown in the following figure.TBSYNC is active high on ...
Page 302 - Figure 12-7. MII Receive Functional Timing
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 302 of 344 In Half-Duplex (DTE) Mode, the DS33R11 supports CRS and COL signals. CRS is active when the PHY detects transmit or receive activity. If there is a collision as indicated by the COL input, the DS33R11 will replace the data nibbl...
Page 303 - Figure 12-9. RMII Receive Interface Functional Timing; Transceiver T1 Mode Functional Timing
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 303 of 344 RMII Receive data on RXD[1:0] is expected to be synchronous with the rising edge of the 50 MHz REF_CLK. The data is only valid if CRS_DV is high. The external PHY asynchronously drives CRS_DV low during carrier loss. Figure 12-9...
Page 305 - RSYNC
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 305 of 344 Figure 12-14. Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled) RSER O CHANNEL 1 RCHCLK RCHBLK RSYSCLK RSYNC CHANNEL 31 CHANNEL 32 1 3 4 RSYNC 2 RMSYNC RSIG CHANNEL 31 CHANNEL 32 B A C/A D/B C/A D/B A B CHANNEL 1 LSB...
Page 308 - Mode
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 308 of 344 12.4 E1 Mode Figure 12-20. Receive-Side Timing FRAME# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 RSYNC 1 RSYNC RFSYNC 2 NOTE 1: RSYNC IN FRAME MODE (TR.IOCR1.5 = 0). NOTE 2: RSYNC IN MULTIFRAME MODE (TR.IOCR1.5 = 1). NOTE 3: THIS ...
Page 313 - 3 OPERATING PARAMETERS; ABSOLUTE MAXIMUM RATINGS; Table 13-1. Recommended DC Operating Conditions
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 313 of 344 13 OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Lead with Respect to V SS (except V DD )….………………………………………..-0.5V to +5.5V Supply Voltage (VDD3.3) Range with Respect to V SS ……………..……………………………………….-0.3V to +...
Page 314 - Thermal Characteristics; PARAMETER MIN; AIR FLOW
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 314 of 344 13.1 Thermal Characteristics Table 13-3. Thermal Characteristics PARAMETER MIN TYP MAX Ambient Temperature (Note 1) -40°C +85°C Junction Temperature (Note 2) +125°C Theta-JA ( θ JA ) in Still Air for 256-Pin 27mm BGA (Notes 2, 3...
Page 315 - PARAMETER SYMBOL; Period; Figure 13-1. Transmit MII Interface Timing
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 315 of 344 13.2 MII Interface Table 13-5. Transmit MII Interface (Note 1, Figure 13-1 ) 10Mbps 100Mbps PARAMETER SYMBOL MIN TYP MAX MIN TYP MAX UNITS TX_CLK Period t1 400 40 ns TX_CLK Low Time t2 140 260 14 26 ns TX_CLK High Time t3 140 26...
Page 316 - Figure 13-2. Receive MII Interface Timing
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 316 of 344 Table 13-6. Receive MII Interface (Note 1, Figure 13-2 ) 10Mbps 100Mbps PARAMETER SYMBOL MIN TYP MAX MIN TYP MAX UNITS RX_CLK Period t5 400 40 ns RX_CLK Low Time t6 140 260 14 26 ns RX_CLK High Time t7 140 260 14 26 ns RXD, RX_D...
Page 317 - Figure 13-3. Transmit RMII Interface Timing
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 317 of 344 13.3 RMII Interface Table 13-7. Transmit RMII Interface (Note 1, Figure 13-3 ) 10Mbps 100Mbps PARAMETER SYMBOL MIN TYP MAX MIN TYP MAX UNITS REF_CLK Frequency 50MHz ±50ppm 50MHz ±50ppm REF_CLK Period t1 20 20 ns REF_CLK Low Time...
Page 318 - Figure 13-4. Receive RMII Interface Timing
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 318 of 344 Table 13-8. Receive RMII Interface (Note 1, Figure 13-4 ) 10Mbps 100Mbps PARAMETER SYMBOL MIN TYP MAX MIN TYP MAX UNITS REF_CLK Frequency 50MHz ±50ppm 50MHz ±50ppm MHz REF_CLK Period t1 20 20 ns REF_CLK Low Time t2 7 13 7 13 ns ...
Page 319 - MDC
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 319 of 344 13.4 MDIO Interface Table 13-9. MDIO Interface (Note 1, Figure 13-5 ) PARAMETER SYMBOL MIN TYP MAX UNITS MDC Frequency 1.67 MHz MDC Period t1 540 600 660 ns MDC Low Time t2 270 300 330 ns MDC High Time t3 270 300 330 ns MDC to M...
Page 320 - Transmit WAN Interface; Figure 13-6. Transmit WAN Interface Timing; TCLKE
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 320 of 344 13.5 Transmit WAN Interface Table 13-10. Transmit WAN Interface (Note 1, Figure 13-6 ) PARAMETER SYMBOL MIN TYP MAX UNITS TCLKE Frequency 52 MHz TCLKE Period t1 19.2 ns TCLKE Low Time t2 8 ns TCLKE High Time t3 8 ns TCLKE to TSE...
Page 321 - Receive WAN Interface; Figure 13-7. Receive WAN Interface Timing
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 321 of 344 13.6 Receive WAN Interface Table 13-11. Receive WAN Interface (Note 1, Figure 13-7 ) PARAMETER SYMBOL MIN TYP MAX UNITS RCLKI Frequency 52 MHz RCLKI Period t1 19.2 ns RCLKI Low Time t2 8 ns RCLKI High Time t3 8 ns RSERI Setup Ti...
Page 323 - SDCLKO
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 323 of 344 Figure 13-8. SDRAM Interface Timing SDCLKO (output) SDATA (output) t1 SDATA (input) SRAS, SCAS, SW E, SDCS (output) t2 t3 t5 t6 t7 t8 t10 t9 SDA, SBA (output) SDMASK (output) t4 t12 t11 t14 t13
Page 330 - Figure 13-15. Receive Line Interface Timing
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 330 of 344 Figure 13-15. Receive Line Interface Timing t F t R RPOSI, RNEGI RDCLKI CL t t CP CH t t SU t HD t DD RPOSO, RNEGO RDCLKO LL t t LP LH t
Page 331 - AC Characteristics: Backplane Clock Timing; Delay RCLKO to BPCLK; Figure 13-16. Receive Timing Delay RCLKO to BPCLK; BPCLK
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 331 of 344 13.10 AC Characteristics: Backplane Clock Timing Table 13-15. AC Characteristics: Backplane Clock Synthesis (V DD = 3.3V ± 5%, T A = -40°C to +85°C.) (Note 1, ( Figure 13-16 ) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Delay ...
Page 332 - AC Characteristics: Transmit Side
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 332 of 344 13.11 AC Characteristics: Transmit Side Table 13-16. AC Characteristics: Transmit Side (V DD = 3.3V ± 5%, T A = 0°C to +85°C.) (Note 1, Figure 13-17 , Figure 13-18 , and Figure 13-19 ) PARAMETER SYMBOL CONDITIONS MIN TYP (E1) MA...
Page 334 - Figure 13-19. Transmit Line Interface Timing
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 334 of 344 Figure 13-18. Transmit-Side Timing, Elastic Store Enabled t F t R TSYSCLK TSERI TCHCLK t t SL t SH SP TSSYNC TCHBLK t D3 t D3 t t t SU HD SU t HD NOTE 1: TSERI IS ONLY SAMPLED ON THE FALLING EDGE OF TSYSCLK WHEN THE TRANSMIT-SID...
Page 335 - JTAG Interface Timing; Figure 13-20. JTAG Interface Timing Diagram
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 335 of 344 13.12 JTAG Interface Timing Table 13-17. JTAG Interface Timing (VDD3.3 = 3.3V ± 5%,VDD1.8 = 1.8V ± 5%, T j = -40°C to +85°C.) (Note 1, Figure 13-20 ) PARAMETER SYMBOL MIN TYP MAX UNITS JTCLK Clock Period t1 1000 ns JTCLK Clock H...
Page 336 - 4 JTAG INFORMATION; . The DS33R11 contains the following as; Figure 14-1. JTAG Functional Block Diagram
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 336 of 344 14 JTAG INFORMATION The DS33R11 contains two JTAG ports. Port 1 is for the Ethernet Mapper, and Port 2 is for the T1/E1/J1 Transceiver. Because of this, this device requires special consideration during JTAG test design. For mor...
Page 337 - JTAG TAP Controller State Machine Description; TAP Controller State Machine; for a diagram of the state machine operation.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 337 of 344 14.1 JTAG TAP Controller State Machine Description This section covers the details on the operation of the Test Access Port (TAP) Controller State Machine. The TAP controller is a finite state machine that responds to the logic ...
Page 340 - BYPASS
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 340 of 344 Table 14-1. Instruction Codes for IEEE 1149.1 Architecture INSTRUCTION SELECTED REGISTER INSTRUCTION CODES SAMPLE:PRELOAD Boundary Scan 010 BYPASS Bypass 111 EXTEST Boundary Scan 000 CLAMP Bypass 011 HIGHZ Bypass 100 IDCODE Devi...
Page 341 - Ethernet
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 341 of 344 14.3 JTAG ID Codes Table 14-2. ID Code Structure DEVICE REVISION ID[31:28] DEVICE CODE ID[27:12] MANUFACTURER’S CODE ID[11:1] REQUIRED ID[0] Ethernet Mapper 0000 0000 0000 0110 0001 000 1010 0001 1 T1/E1/J1 Transceiver 0000 0000...
Page 342 - JTAG Functional Timing; This functional timing for the JTAG circuits shows:
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 342 of 344 14.5 JTAG Functional Timing This functional timing for the JTAG circuits shows: • The JTAG controller starting from reset state. • Shifting out the first 4 LSB bits of the IDCODE. • Shifting in the BYPASS instruction (111) while...
Page 343 - 5 PACKAGE INFORMATION
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 343 of 344 15 PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. The package number provided for each package is a link to the latest package outline information.) 15.1 256-Ball ...
Page 344 - 6 DOCUMENT REVISION HISTORY; REVISION DESCRIPTION; New product release.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 344 of 344 Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor ...
