Fujitsu MHV2100BH - Manual

C141-E224 i Preface This manual describes MHV2100BH, MHV2080BH, MHV2060BH, MHV2040BH model of the MHV Series, 2.5-inch hard disk drives. These drives have a built-in controller that is compatible with the Serial-ATA interface. This manual describes the specifications and functions of the drives and ...

Preface ii C141-E224 Conventions for Alert Messages This manual uses the following conventions to show the alert messages. An alert message consists of an alert signal and alert statements. The alert signal consists of an alert symbol and a signal word or just a signal word. The following are the al...

Preface C141-E224 iii Attention Please forward any comments you may have regarding this manual. To make this manual easier for users to understand, opinions from readers are needed. Please write your opinions or requests on the Comment at the back of this manual and forward it to the address describ...

C141-E224 v Important Alert Items Important Alert Messages The important alert messages in this manual are as follows: A hazardous situation could result in minor or moderate personal injury if the user does not perform the procedure correctly. Also, damage to the product or other property, may occu...

C141-E224 vii Manual Organization MHV2100BH, MHV2080BH MHV2060BH, MHV2040BH DISK DRIVES PRODUCT MANUAL (C141-E224) <This manual> • Device Overview • Device Configuration • Installation Conditions • Theory of Device Operation • Interface • Operations MHV2100BH, MHV2080BH MHV2060BH, MHV2040BH DI...

C141-E224 ix Contents CHAPTER 1 Device Overview ........................................................................ 1-1 1.1 Features .............................................................................................................. 1-2 1.1.1 Functions and performance ..................

Contents x C141-E224 CHAPTER 2 Device Configuration ................................................................ 2-1 2.1 Device Configuration ....................................................................................... 2-2 2.2 System Configuration ........................................

Contents C141-E224 xi 4.6 Read/write Circuit .............................................................................................. 4-9 4.6.1 Read/write preamplifier (PreAMP) ......................................................... 4-9 4.6.2 Write circuit.......................................

Contents xiv C141-E224 5.4.5 DMA data-out command protocol ................................................... 5-152 5.4.6 Native Command Queuing protocol ................................................ 5-153 5.5 Power-on and COMRESET ...................................................................

Contents xvi C141-E224 Illustrations Figures Figure 1.1 Negative voltage at +5 V when power is turned off ............................ 1-6 Figure 1.2 Current fluctuation (Typ.) at +5 V when power is turned on .............. 1-8 Figure 2.1 Disk drive outerview............................................

Contents xviii C141-E224 Tables Table 1.1 Specifications ....................................................................................... 1-4 Table 1.2 Examples of model names and product numbers ................................. 1-5 Table 1.3 Current and power dissipation ......................

C141-E224 1-1 CHAPTER 1 Device Overview 1.1 Features 1.2 Device Specifications 1.3 Power Requirements 1.4 Environmental Specifications 1.5 Acoustic Noise 1.6 Shock and Vibration 1.7 Reliability 1.8 Error Rate 1.9 Media Defects 1.10 Load/Unload Function 1.11 Advanced Power Management (APM) 1.12 Inter...

Device Overview 1-4 C141-E224 1.2 Device Specifications 1.2.1 Specifications summary Table 1.1 shows the specifications of the disk drives. Table 1.1 Specifications (1 of 2) MHV2100BH MHV2080BH MHV2060BH MHV2040BH Format Capacity (*1, *2) 100 GB 80 GB 60 GB 40 GB Number of Sectors (User) 195,371,568...

1.2 Device Specifications C141-E224 1-5 Table 1.1 lists the formatted capacity, number of logical cylinders, number of heads, and number of sectors of every model for which the CHS mode has been selected using the BIOS setup utility on the host. Table 1.1 Specifications (2 of 2) Model Capacity No. o...

Device Overview 1-6 C141-E224 1.3 Power Requirements (1) Input Voltage • + 5 V ± 5 % • It is unnecessary for this drive to supply +3.3 V and +12 V power supplies. (2) Ripple +5 V Maximum 100 mV (peak to peak) Frequency DC to 1 MHz (3) A negative voltage like the bottom figure isn't to occur at +5 V ...

1.3 Power Requirements C141-E224 1-7 (4) Current Requirements and Power Dissipation Table 1.3 lists the current and power dissipation (typical). Table 1.3 Current and power dissipation Typical RMS Current Typical Power (*3) Spin up (*1) 1.0 A 5.0 W Idle (*6) 120 mA 0.60 W R/W (on track) (*2) 380 mA ...

Device Overview 1-8 C141-E224 (5) Current fluctuation (Typ.) at +5 V when power is turned on Figure 1.2 Current fluctuation (Typ.) at +5 V when power is turned on (6) Power on/off sequence The voltage detector circuits monitor +5 V. The circuits do not allow a write signal if either voltage is abnor...

1.5 Acoustic Noise C141-E224 1-9 1.5 Acoustic Noise Table 1.5 lists the acoustic noise specification. Table 1.5 Acoustic noise specification Item Specification (typical) • Idle mode (DRIVE READY) Sound Power 2.2 B [MHV2040BH] 2.6 B [MHV2100BH/MHV2080BH/MHV2060BH] Sound Pressure (at 0.3m) 22 dB [MHV2...

Device Overview 1-12 C141-E224 Emergency Unload other than Unload is performed when the power is shut down while the heads are still loaded on the disk. The product supports the Emergency Unload a minimum of 20,000 times. When the power is shut down, the controlled Unload cannot be executed. Therefo...

1.11 Advanced Power Management C141-E224 1-13 Low Power Idle: The head is unloaded from disk. The spindle motor rotates. Standby: The spindle motor stops. In APM Mode-1, which is the APM default mode, the operation status shifts till it finally reaches "Low Power Idle." Table 1.7 Advanced Po...

1.13 Elimination of Hazardous Substances C141-E224 1-15 Table 1.8 Interface power management IPM Mode I/F power state Return time to active I/F condition Active Active State − Active Partial Partial State 5 to 10 µ s maximum Power Down Slumber Slumber State 5 to 10 ms maximum Power Down 1.13 Elimina...

C141-E224 2-1 CHAPTER 2 Device Configuration 2.1 Device Configuration 2.2 System Configuration This chapter describes the internal configurations of the hard disk drives and the configuration of the systems in which they operate.

Device Configuration 2-2 C141-E224 2.1 Device Configuration Figure 2.1 shows the disk drive. The disk drive consists of a disk enclosure (DE), read/write preamplifier, and controller PCA. The disk enclosure contains the disk media, heads, spindle motors, actuators, and a circulating air filter. Figu...

2.2 System Configuration C141-E224 2-3 (6) Read/write circuit The read/write circuit uses a LSI chip for the read/write preamplifier. It improves data reliability by preventing errors caused by external noise. (7) Controller circuit The controller circuit supports Serial-ATA interface, and it realiz...

C141-E224 3-1 CHAPTER 3 Installation Conditions 3.1 Dimensions 3.2 Mounting 3.3 Cable Connections This chapter gives the external dimensions, installation conditions, surface temperature conditions, cable connections, and switch settings of the hard disk drives.

Installation Conditions 3-2 C141-E224 3.1 Dimensions Figure 3.1 illustrates the dimensions of the disk drive. All dimensions are in mm. *1 The PCA and connectors are not included in these dimensions. *2 Dimension from the center of the user tap to the base of the connector pins *3 Length of the conn...

3.2 Mounting C141-E224 3-3 3.2 Mounting For information on mounting, see the "FUJITSU 2.5-INCH HDD INTEGRATION GUIDANCE (C141-E144)." (1) Orientation Figure 3.2 illustrates the allowable orientations for the disk drive. (a) Horizontal –1 (b) Horizontal –2 (c) Vertical –1 (d) Vertical –2 (e) ...

Installation Conditions 3-4 C141-E224 (2) Frame The MR head bias of the HDD disk enclosure (DE) is zero. The mounting frame is connected to Signal Ground (SG). IMPORTANT Use M3 screw for the mounting screw and the screw length should satisfy the specification in Figure 3.3. The tightening torque mus...

3.2 Mounting C141-E224 3-5 IMPORTANT Because of breather hole mounted to the HDD, do not allow this to close during mounting. Locating of breather hole is shown as Figure 3.4. For breather hole of Figure 3.4, at least, do not allow its around φ 2.4 to block. Figure 3.4 Location of breather

Installation Conditions 3-6 C141-E224 (4) Ambient temperature The temperature conditions for a disk drive mounted in a cabinet refer to the ambient temperature at a point 3 cm from the disk drive. The ambient temperature must satisfy the temperature conditions described in Section 1.4, and the airfl...

3.2 Mounting C141-E224 3-7 (5) Service area Figure 3.6 shows how the drive must be accessed (service areas) during and after installation. Mounting screw hole Mounting screw hole Cable connection Figure 3.6 Service area Data corruption: Avoid mounting the disk drive near strong magnetic sources such...

Installation Conditions 3-8 C141-E224 - General notes Figure 3.7 Handling cautions - Installation (1) Please use the driver of a low impact when you use an electric driver. HDD is occasionally damaged by the impact of the driver. (2) Please observe the tightening torque of the screw strictly. M3 ···...

3.3 Connections with Host System C141-E224 3-9 3.3 Connections with Host System 3.3.1 Device connector The disk drive has the SATA interface connectors listed below for connecting external devices. Figure 3.8 shows the locations of these connectors and terminals. SATA interface and power connectors ...

Installation Conditions 3-10 C141-E224 3.3.2 Signal segment and power supply segment Figure 3.9 shows each segment of the SATA interface connector and pin numbers. Power supply segment P1 pins in the power supply segment S1 pins in the signal segment View from the connector side View from the PCA si...

3.3 Connections with Host System C141-E224 3-11 3.3.4 SATA interface cable connection The cable that connects the disk drive to the host system must be compliant with the Serial ATA 1.0a specification. 3.3.5 Note about SATA interface cable connection Take note of the following precaution about plugg...

C141-E224 4-1 CHAPTER 4 Theory of Device Operation 4.1 Outline 4.2 Subassemblies 4.3 Circuit Configuration 4.4 Power-on Sequence 4.5 Self-calibration 4.6 Read/write Circuit 4.7 Servo Control This chapter explains basic design concepts of the disk drive. Also, this chapter explains subassemblies of t...

4.3 Circuit Configuration C141-E224 4-3 4.2.4 Air filter There are two types of air filters: a breather filter and a circulation filter. The breather filter makes an air in and out of the DE to prevent unnecessary pressure around the spindle when the disk starts or stops rotating. When disk drives a...

Theory of Device Operation 4-4 C141-E224 (4) Controller circuit Major functions are listed below. • Serial-ATA interface control and data transfer control • Data buffer management • Sector format control • Defect management • ECC control • Error recovery and self-diagnosis Figure 4.1 Power supply co...

4.3 Circuit Configuration C141-E224 4-5 MCU & HDC & RDC HDC MCU RDC Data Buffer SDRAM Serial Flash ROM SVC Crystal 40MHz R/W Pre-Amp Thermist VCM HEAD SP Motor Media DE PCA Serial-ATA Interface Shock Sensor Console Micro-DSP Figure 4.2 Circuit configuration

4.5 Self-calibration C141-E224 4-7 4.5 Self-calibration The disk drive occasionally performs self-calibration in order to sense and calibrate mechanical external forces on the actuator, and VCM torque. This enables precise seek and read/write operations. 4.5.1 Self-calibration contents (1) Sensing a...

4.6 Read/write Circuit C141-E224 4-9 4.6 Read/write Circuit The read/write circuit consists of the read/write preamplifier (PreAMP), the write circuit, the read circuit, and the time base generator in the read channel (RDC) block which is integrated into LSI. Figure 4.4 is a block diagram of the rea...

Theory of Device Operation 4-10 C141-E224 4.6.3 Read circuit The head read signal from the PreAMP is regulated by the automatic gain control (AGC) circuit. Then the output is converted into the sampled read data pulse by the programmable filter circuit and the flash digitizer circuit. This signal is...

Theory of Device Operation 4-12 C141-E224 4.7 Servo Control The actuator motor and the spindle motor are submitted to servo control. The actuator motor is controlled for moving and positioning the head to the track containing the desired data. To turn the disk at a constant velocity, the actuator mo...

4.7 Servo Control C141-E224 4-15 4.7.2 Data-surface servo format Figure 4.7 describes the physical layout of the servo frame. The three areas indicated by (1) to (3) in Figure 4.7 are described below. (1) Inner guard band This area is located inside the user area, and the rotational speed of the VCM...

Theory of Device Operation 4-16 C141-E224 Figure 4.7 Physical sector servo configuration on disk surface

4.7 Servo Control C141-E224 4-17 4.7.3 Servo frame format As the servo information, the IDD uses the phase signal servo generated from the gray code and servo EVEN and ODD. This servo information is used for positioning operation of radius direction and position detection of circumstance direction. ...

C141-E224 5-1 CHAPTER 5 Interface 5.1 Physical Interface 5.2 Logical Interface 5.3 Host Commands 5.4 Command Protocol 5.5 Power-on and COMRESET This chapter gives details about the interface, and the interface commands and timings.

Interface 5-2 C141-E224 5.1 Physical Interface 5.1.1 Interface signals Figure 5.1 shows the interface signals. +5VDC TX data RX data ComWake ComInit TX data RX data ComWake ComReset TX+ TX − TX+ TX − RX+ RX+ RX − RX − Host analog front end Device analog front end GND Figure 5.1 Interface signals An ...

5.1 Physical Interface C141-E224 5-5 5.1.2.2 Primitives descriptions The following table contains the primitive mnemonics and a brief description of each. Primitive Name Description ALIGN Physical layer control Upon receipt of an ALIGN, the physical layer readjusts internal operations as necessary t...

Interface 5-10 C141-E224 5.1.4 Connector pinouts The pin definitions are shown in Table 5.2. Table 5.2 Connector pinouts Signal segment key S1 Gnd 2nd mate S2 A+ S3 A- Differential signal pair A from Phy S4 Gnd 2nd mate S5 B- Differential signal pair B from Phy S6 B+ Signal segment S7 Gnd 2nd mate “...

5.1 Physical Interface C141-E224 5-11 5.1.5 P11 function The disk drive supports the following functions when P11 pin in the power supply segment of interface connector is used as an input or output pin. P11 pin supports the functions as follows: • Staggered Spin-up: Use P11 as an input pin • Drivin...

Interface 5-12 C141-E224 Figure 5.2 Example of the circuit for driving Ready LED

Interface 5-14 C141-E224 5.2 Logical Interface The host system and the device communicate with each other by sending and receiving serial data. The host and the device have several dedicated communication layers between them. These layers have different functions, enabling communication between the ...

5.2 Logical Interface C141-E224 5-15 5.2.1 Communication layers Each of the layers is outlined below. Physical layer • Detects, sends, and receives band signals. • Sends serial data to and receives it from the link layer. Link layer • Negotiates against mutual transfer requests between the host syst...

Interface 5-16 C141-E224 5.2.2 Outline of the Shadow Block Register Each transport layer in the host system and device has a block register, which is called a Shadow Block Register in the host system, and a Block Register in the device. These registers are used when the host system issues a command ...

5.2 Logical Interface C141-E224 5-17 5.2.3 Outline of the frame information structure (FIS) The transport layer converts data written in a Block Register into the FIS, and sends it to the upper layer. The FIS, which is generated in the transport layer, is explained below. 5.2.3.1 FIS types The types...

Interface 5-18 C141-E224 The host system uses the Register - Host to Device FIS when information in the Register Block is transferred from the host system to the device. This is the mechanism for issuing the ATA command from the host system to the device. C - To update the Command field, "1"...

5.2 Logical Interface C141-E224 5-19 The host uses the DMA Active - Device to Host FIS layout. This FIS instructs the host to continue transferring DMA data from the host to the device. 5.2.3.5 DMA Setup - Device to Host or Host to Device (Bidirectional) The DMA Setup - Device to Host or Host to Dev...

Interface 5-20 C141-E224 5.2.3.6 BIST Active - Bidirectional The BIST Active - Bidirectional FIS has the following layout: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved (0) Pattern definition R R R Reserved (0) FIS Type (58h) 0 T A S L F P R V Data [3...

5.3 Host Commands C141-E224 5-31 (1) RECALIBRATE (X’10’ to X’1F’) This command performs the calibration. When the device completes the calibration, the device reports the status to the host system. This command can be issued in the LBA mode. • Error reporting conditions (1) An error was detected dur...

5.3 Host Commands C141-E224 5-41 (7) EXECUTE DEVICE DIAGNOSTIC (X’90’) This command performs an internal diagnostic test (self-diagnosis) of the device. The device reports the diagnostic result and status to the host. Table 5.7 lists the diagnostic code written in the Error field which is 8-bit code...

5.3 Host Commands C141-E224 5-43 (9) DOWNLOAD MICROCODE (X’92’) At command issuance (Shadow Block Registers setting contents) CM 1 0 0 1 0 0 1 0 DH 1 x 1 x 0 0 0 0 CH 00 CL 00 SN Sector count (15-8) SC Sector count (7-0) FR Subcommand code At command completion (Shadow Block Registers contents to be...

Interface 5-44 C141-E224 **: In the following cases, Subcommand code=07h returns Abort as an error though becomes Microcode rewriting execution specification. 1) Abnormality of the transmitted Microcode data is detected. 2) The data transfer is not done (The number of transfer: 0). 3) The DOWNLOAD M...

Interface 5-60 C141-E224 Table 5.13 Off-line data collection status Status Byte Meaning 00h or 80h Off-line data collection is not executed. 02h or 82h Off-line data collection has ended without an error. 04h or 84h Off-line data collection is interrupted by a command from the host. 05h or 85h Off-l...

5.3 Host Commands C141-E224 5-61 • Off-line data collection capability Indicates the method of off-line data collection carried out by the drive. If the off-line data collection capability is 0, it indicates that off-line data collection is not supported. Table 5.15 Off-line data collection capabili...

Interface 5-62 C141-E224 • Checksum Two’s complement of the lower byte, obtained by adding 511-byte data one byte at a time from the beginning. • Guarantee failure threshold The limit of a varying attribute value. The host compares the attribute values with the thresholds to identify a failure. Tabl...

5.3 Host Commands C141-E224 5-65 Table 5.20 Data format of SMART Comprehensive Error Log Byte First sector Next sector 00 SMART Error Logging 01h Reserved 01 Index Pointer Latest Error Data Structure Reserved 02…5B 1 st Error Log Data Structure Error Log Data Structure 5n+1 5C…B5 2 nd Error Log Data...

Interface 5-66 C141-E224 Table 5.21 SMART self-test log data format Byte Item 00, 01 Self-test log data structure 02 Self-test number (Sector Number field Value) 03 Self-test execution status 04, 05 Life time. Total power-on time [hours] 06 Self-test error No. 07 to 0A Error LBA 0B to 19 Self-test l...

5.3 Host Commands C141-E224 5-67 Table 5.22 Selective self-test log data structure Byte Item 00h, 01h Data Structure Revision Number 02h...09h Starting LBA 0Ah...11h Test Span 1 Ending LBA 12h...19h Starting LBA 1Ah...21h Test Span 2 Ending LBA 22h...29h Starting LBA 2Ah...31h Test Span 3 Ending LBA...

Interface 5-68 C141-E224 • Current Span under test As the self-test progress, the device shall modify this value to contain the test span number currently being tested. • Feature Flags Table 5.23 Selective self-test feature flags Bit Description 0 Vendor specific (unused) 1 When set to one, perform ...

5.3 Host Commands C141-E224 5-75 Host Reg. HD PIO Setup PIO Setup PIO Setup Data (1sector) Data (4 sectors) Device Data (4 sectors) Block Block Partial Block Figure 5.10 Execution example of READ MULTIPLE command • Error reporting conditions (1) A specified address exceeds the range where read opera...

5.3 Host Commands C141-E224 5-103 At command completion (Shadow Block Registers contents to be read) ST Status information DH x x x x xx CH CL SN SC E xx xx xx xx Error information *1) Data Transfer Mode The host sets X’03’ to the Features field. By issuing this command with setting a value to the S...

5.3 Host Commands C141-E224 5-105 *3) Serial ATA Functions The host can enable and disable the following Serial ATA functions by issuing this command after setting X'10/90' in the Features field and an applicable value in the Sector Count field: Serial ATA function Sector Count field Non-zero buffer...

Interface 5-106 C141-E224 (29) SECURITY SET PASSWORD (X’F1’) This command enables a user password or master password to be set. The host transfers the 512-byte data shown in Table 5.27 to the device. The device determines the operation of the lock function according to the specifications of the Iden...

Interface 5-114 C141-E224 (34) SECURITY DISABLE PASSWORD (X’F6’) This command invalidates the user password already set and releases the lock function. The host transfers the 512-byte data shown in Table 5.29 to the device. The device compares the user password or master password in the transferred ...

5.3 Host Commands C141-E224 5-117 (36) SET MAX (X’F9’) SET MAX Features Register Values Value Command 00h Obsolete 01h SET MAX SET PASSWORD 02h SET MAX LOCK 03h SET MAX UNLOCK 04h SET MAX FREEZE LOCK 05h - FFh Reserved • SET MAX ADDRESS A successful READ NATIVE MAX ADDRESS command shall immediately ...

Interface 5-130 C141-E224 Table 5.32 Data format of Read Log Ext log page 11h Byte Item 00 to 03 Reserved 04 to 05 Counter 1 Identifier 06 to 09 Counter 1 Value 0A to 0B Counter 2 Identifier 0C to 0F Counter 2 Value … … 4C to 4D Counter 10 Identifier 4E to 51 Counter 10 Value 52 to 53 Counter 0 Iden...

5.3 Host Commands C141-E224 5-141 (50) WRITE DMA FUA EXT (X'3D') • Description The WRITE DMA FUA EXT command reports the status of a command after user data is written to a medium, regardless of whether the write cache feature is enabled or disabled. The other command control and error reporting con...

Interface 5-146 C141-E224 5.4 Command Protocol The host should confirm that the BSY bit of the Shadow Block Status register of the device is 0 prior to issue a command. If BSY bit is 1, the host should wait for issuing a command until BSY bit is cleared to 0. Commands can be executed only when the D...

5.4 Command Protocol C141-E224 5-147 • READ NATIVE MAX ADDRESS (EXT) • IDLE • IDLE IMMEDIATE • STANDBY • STANDBY IMMEDIATE • CHECK POWER MODE • SMART DISABLE OPERATION • SMART ENABLE/DISABLE AUTOSAVE • SMART ENABLE OPERATION • SMART EXECUTE OFFLINE IMMEDIATE • SMART RETURN STATUS • SECURITY ERASE PR...

5.4 Command Protocol C141-E224 5-149 Device Host RegHD PIO Setup DATA Figure 5.12 PIO data-in command protocol 5.4.3 PIO data-out command protocol Execution of the following commands involves data transfers from the host system to the device: • WRITE SECTOR(S) (EXT) • WRITE MULTI (EXT) (FUA EXT) • W...

Interface 5-150 C141-E224 An outline of this protocol is as follows: 1) The device receives a PIO data-out command with the RegHD FIS. 2) If an error remaining in the device prevents command execution, the device sends the RegDH FIS with 1 set in the I bit. 3) When the device is ready to receive dat...

5.4 Command Protocol C141-E224 5-151 5.4.4 DMA data-in command protocol DMA data-in commands include the following commands: • READ DMA (EXT) • IDENTFY DEVICE • IDENTFY DEVICE DMA The DMA mechanism transfers data of more than one block from the device to the host. The completion of a command is repo...

Interface 5-152 C141-E224 5.4.5 DMA data-out command protocol The DMA data-out command is the following command: • WRITE DMA (EXT) (FUA EXT) The DMA mechanism transfers data of more than one block from the host to the device. The completion of the command is reported by an interruption. An outline o...

Interface 5-154 C141-E224 8) If an uncorrectable error occurs during command queuing, the device sends to the host the Set Device Bits FIS with the settings of ERR bit = 1, ERRReg = ATAErrCode, I bit = 1, and SActive = 0 to report an error. 9) After reporting the error, the device accepts only the R...

5.4 Command Protocol C141-E224 5-155 Device Host RegHD RegDH DMA Setup SetDB DATA DMACT Figure 5.17 WRITE FP DMA QUEUED command protocol

5.5 Power-on and COMRESET C141-E224 5-157 Device TX (Host RX) Host TX(Device RX) Host/device on Host ComReset Host releases Com Reset Host calibrate Host ComW ake Host releases ComW ake Host Align Host data Device ComInit Device releases ComInit Device Calibrate Device ComW ake Device Align Device d...

C141-E224 6-1 CHAPTER 6 Operations 6.1 Reset and Diagnosis 6.2 Power Save 6.3 Interface Power Save 6.4 Read-ahead Cache 6.5 Write Cache This chapter explains each of the above operations.

Operations 6-2 C141-E224 6.1 Reset and Diagnosis This section explains the device responses to power-on and an accepted reset. 6.1.1 Response to power-on Immediately after power is turned on, the host sets 0x7Fh in the Status field of the Shadow Block and 0xFFh in other fields. After communication w...

6.1 Reset and Diagnosis C141-E224 6-3 Figure 6.2 Response to power-on (when the device is powered on earlier than the host)

Operations 6-4 C141-E224 6.1.2 Response to COMRESET The response to COMRESET is almost the same as the response when power is turned on and a power-on reset is then cancelled. The device establishes communication with the SATA interface (PHY Ready) and sends the RegDH FIS (STS = 50h) to notify the h...

6.1 Reset and Diagnosis C141-E224 6-7 6.1.3 Response to a software reset When a software reset is accepted, the device performs a self-diagnosis, and it sends the RegDH FIS (STS = 50h) to notify the host that the device is ready. Then, the software reset sequence is completed. Figure 6.4 Response to...

6.3 Power Save Controlled by Interface Power Management (IPM) C141-E224 6-11 6.3 Power Save Controlled by Interface Power Management (IPM) The host system can change the power consumption status of the interface by issuing the PARTIAL or SLUMBER request to the device. 6.3.1 Power save mode of the in...

6.4 Read-ahead Cache C141-E224 6-13 6.4 Read-ahead Cache Read-ahead Cache is the function for automatically reading data blocks upon completion of the read command in order to read data from disk media and save data block on a data buffer. If a subsequent command requests reading of the read-ahead d...

6.4 Read-ahead Cache C141-E224 6-17 6.4.3.2 Sequential hit When the read command that is targeted at a sequential address is received after execution of the read commands is completed, the read command transmits the Read requested data to the host system continuing read-ahead without newly allocatin...

C141-E224 GL-1 Glossary Actuator Head positioning assembly. The actuator consists of a voice coil motor and head arm. If positions the read-write (R-W) head. AT bus A bus between the host CPU and adapter board ATA (AT Attachment) standard The ATA standard is for a PC AT interface regulated to establ...

Glossary C141-E224 GL-3 Rotational delay Time delay due to disk rotation. The mean delay is the time required for half a disk rotation. The mean delay is the average time required for a head to reach a sector after the head is positioned on a track. Seek time The seek time is the time required for a...

C141-E224 AB-1 Acronyms and Abbreviations A ABRT Aborted command AIC Automatic idle control AMNF Address mark not found ATA AT attachment AWG American wire gage B BBK Bad block detected BIOS Basic input-output system C CORR Corrected data CH Cylinder high register CL Cylinder low register CM Command...

C141-E224 IN-1 Index A A/D converter circuit ............................... 4-11 AAM...................................................... 5-105 acceleration mode .................................... 4-20 acoustic noise ............................................ 1-9 acoustic noise specification ....

C141-E224-01EN Comment Form We would appreciate your comments and suggestions regarding this manual. Manual code C141-E224-01EN Manual name MHV2100BH, MHV2080BH, MHV2060BH, MHV2040BH DISK DRIVES PRODUCT MANUAL Please mark each item: E(Excellent), G(Good), F(Fair), P(Poor). General appearance ( ) Tec...