Epson ARM720T - Manual - manualsarea.com

Page 2 - NOTICE

NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permis-sion of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. SeikoEpson does not assume any liability of any kind arising out of any inaccura...

Page 5 - ARM; Contents

CONTENTS ARM 720T CORE CPU MANUAL EPSON i Contents Preface About this document................................................................................................ xi 1 Introduction 1.1 About the ARM720T processor ................................................................. 1-1 1.2 C...

Page 6 - ii EPSON; Memory Management Unit

CONTENTS ii EPSON ARM720T CORE CPU MANUAL 6.9 Reset ....................................................................................................... 6-13 7 Memory Management Unit 7.1 About the MMU .......................................................................................... 7-1 7...

Page 7 - ARM720T CORE CPU MANUAL; 0 ETM Interface; Signal Descriptions; Glossary

CONTENTS ARM720T CORE CPU MANUAL EPSON iii 10 ETM Interface 10.1 About the ETM interface .......................................................................... 10-1 10.2 Enabling and disabling the ETM7 interface ............................................. 10-1 10.3 Connections between the ETM7...

Page 8 - iv EPSON; List of Figures

CONTENTS iv EPSON ARM720T CORE CPU MANUAL List of Figures Figure 1-1 720T Block diagram .................................................................................... 1-2 Figure 1-2 ARM720T processor functional signals....................................................... 1-3 Figure 1-3 ARM i...

Page 10 - vi EPSON; List of Tables

CONTENTS vi EPSON ARM720T CORE CPU MANUAL List of Tables Table 1-1 Key to tables ............................................................................................... 1-6 Table 1-2 ARM instruction summary ........................................................................... 1-8 Table...

Page 13 - Preface

Page 15 - About this document; Intended audience

Preface ARM720T CORE CPU MANUAL EPSON xi Preface This preface introduces the ARM720T Revision 4 (AMBA AHB Bus Interface Version) CORE CPU Manual . It contains the following sections: About this document ....................................................................................................

Page 16 - xii; Typographical conventions; monospace; monospace bold; Product revision status

Preface xii EPSON ARM720T CORE CPU MANUAL Chapter 8 Coprocessor Interface Read this chapter for a description on how to connect coprocessors to the ARM1156F-S coprocessor interface. Chapter 9 Debugging Your System Read this chapter for a description of the hardware extensions and integrated on-chip ...

Page 17 - Timing diagram conventions; Further reading; ARM publications; following documents for other relevant information:; ARM Architecture Reference Manual; Other publications; Standard Test Access Port and Boundary Scan Architecture

Preface ARM720T CORE CPU MANUAL EPSON xiii Timing diagram conventions This manual contains one or more timing diagrams. The following key explains the components used in these diagrams. Any variations are clearly labeled when they occur. Therefore, no additional meaning must be attached unless speci...

Page 18 - xiv

Preface xiv EPSON ARM720T CORE CPU MANUAL THIS PAGE IS BLANK.

Page 19 - Introduction

Page 21 - About the ARM720T processor; or; Direct Memory Access; with microprogrammed; Complex Instruction Set Computers

1: Introduction ARM720T CORE CPU MANUAL EPSON 1-1 1 Introduction This chapter provides an introduction to the ARM720T processor. It contains the following sections: 1.1 About the ARM720T processor .................................................................. 1-1 1.2 Coprocessors ..................

Page 23 - Debug Communications Channel; logic is controlled through the; Joint Test Action Group

1: Introduction ARM720T CORE CPU MANUAL EPSON 1-3 The functional signals on the ARM720T processor are shown in Figure 1-2. Figure 1-2 ARM720T processor functional signals 1.1.1 EmbeddedICE-RT logic The EmbeddedICE-RT logic provides integrated on-chip debug support for the ARM720T core. It enables yo...

Page 24 - Changes to the programmer’s model; Debug control register

1: Introduction 1-4 EPSON ARM720T CORE CPU MANUAL Changes to the programmer’s model To provide support for the EmbeddedICE-RT macrocell, the following changes have been made to the programmer’s model for the ARM720T processor:Debug Control Register There are two new bits in the Debug Control Registe...

Page 25 - Coprocessors; the device (see Chapter 3; Configuration; About the instruction set; The instruction set comprises ten basic instruction types:

1: Introduction ARM720T CORE CPU MANUAL EPSON 1-5 1.2 Coprocessors The ARM720T processor has an internal coprocessor designated CP15 for internal control of the device (see Chapter 3 Configuration ). The ARM720T processor also includes a port for the connection of on-chip external coprocessors. This...

Page 26 - Format summary; ARM instruction set; Table 1-1 Key to tables

1: Introduction 1-6 EPSON ARM720T CORE CPU MANUAL 1.3.1 Format summary This section provides a summary of the ARM and Thumb instruction sets: • ARM instruction set on page 1-7 • Thumb instruction set on page 1-14 A key to the instruction set tables is shown in Table 1-1.The ARM7TDMI-S core on the AR...

Page 27 - instructions, see the; The ARM instruction set formats are shown in Figure 1-3.

1: Introduction ARM720T CORE CPU MANUAL EPSON 1-7 1.3.2 ARM instruction set This section gives an overview of the ARM instructions available. For full details of these instructions, see the ARM Architecture Reference Manual . The ARM instruction set formats are shown in Figure 1-3. Figure 1-3 ARM in...

Page 30 - Table 1-3 Addressing mode 2

1: Introduction 1-10 EPSON ARM720T CORE CPU MANUAL Addressing mode 2, <a_mode2> , is shown in Table 1-3. Coprocessors Data operations CDP{cond} p<cpnum>, <op1>, <CRd>, <CRn>, <CRm>, <op2> Move to ARM reg from coproc MRC{cond} p<cpnum>, <op1>, <...

Page 31 - Table 1-5 Addressing mode 3

1: Introduction ARM720T CORE CPU MANUAL EPSON 1-11 Addressing mode 2 (privileged), <a_mode2P> , is shown in Table 1-4. Addressing mode 3 (signed byte, and halfword data transfer), <a_mode3> , is shown in Table 1-5. Addressing mode 4 (load), <a_mode4L> , is shown in Table 1-6. Table...

Page 32 - Table 1-8 Addressing mode 5

1: Introduction 1-12 EPSON ARM720T CORE CPU MANUAL Addressing mode 4 (store), <a_mode4S> , is shown in Table 1-7. Addressing mode 5 (coprocessor data transfer), <a_mode5> , is shown in Table 1-8. Operand 2, <Oprnd2> , is shown in Table 1-9. Fields, {field} , are shown in Table 1-10...

Page 34 - Thumb instruction set; The Thumb instruction set formats are shown in Figure 1-4.

1: Introduction 1-14 EPSON ARM720T CORE CPU MANUAL 1.3.3 Thumb instruction set This section gives an overview of the Thumb instructions available. For full details of these instructions, see the ARM Architecture Reference Manual . The Thumb instruction set formats are shown in Figure 1-4. Figure 1-4...

Page 38 - Silicon revisions; This manual is for revision r4p2 of the ARM720T macrocell. See; on

1: Introduction 1-18 EPSON ARM720T CORE CPU MANUAL 1.4 Silicon revisions This manual is for revision r4p2 of the ARM720T macrocell. See Product revision status on page xii for details of revision numbering. There are no functional differences from previous revisions.

Page 39 - Programmer’s Model

Page 41 - Processor operating states; Switching between processor states; Entering Thumb state; Interrupt ReQuest; Entering ARM state

2: Programmer’s Model ARM720T CORE CPU MANUAL EPSON 2-1 2 Programmer’s Model This chapter describes the programmer’s model for the ARM720T processor. It contains the following sections: 2.1 Processor operating states ......................................................................... 2-1 2.2 M...

Page 42 - EPSON; Memory formats; Control Register; Figure 2-1 Big-endian addresses of bytes with words

2: Programmer’s Model 2-2 EPSON ARM720T CORE CPU MANUAL 2.2 Memory formats The ARM720T processor views memory as a linear collection of bytes numbered upwards from zero, as follows: Bytes 0 to 3 Hold the first stored word. Bytes 4 to 7 Hold the second stored word. Bytes 8 to 11 Hold the third stored...

Page 43 - Instruction length

2: Programmer’s Model ARM720T CORE CPU MANUAL EPSON 2-3 2.2.2 Little-endian format In little-endian format, the lowest numbered byte in a word is considered the least significant byte of the word, and the highest numbered byte the most significant. Byte 0 of the memory system is therefore connected ...

Page 44 - Operating modes; Changing operating modes; Registers; The ARM state register set; Branch and Link; Table 2-1 ARM720T modes of operation

2: Programmer’s Model 2-4 EPSON ARM720T CORE CPU MANUAL 2.5 Operating modes The ARM720T processor supports seven modes of operation, as shown in Table 2-1. 2.5.1 Changing operating modes Mode changes can be made under software control, by external interrupts or during exception processing. Most appl...

Page 45 - Interrupt modes; Figure 2-3 Register organization in ARM state

2: Programmer’s Model ARM720T CORE CPU MANUAL EPSON 2-5 Interrupt modes FIQ mode has seven banked registers mapped to r8-14 (r8_fiq-r14_fiq). In ARM state, many FIQ handlers can use these banked registers to avoid having to save any registers onto a stack. User, IRQ, Supervisor, Abort, and Undefined...

Page 46 - The Thumb state register set; the PC; Stack Pointer; Figure 2-4 Register organization in Thumb state

2: Programmer’s Model 2-6 EPSON ARM720T CORE CPU MANUAL 2.6.2 The Thumb state register set The Thumb state register set is a subset of the ARM state set. You have direct access to: • eight general registers, (r0–r7) • the PC • a Stack Pointer (SP) register • a Link Register (LR) • the CPSR. There ar...

Page 47 - The relationship between ARM and Thumb state registers; MOV

2: Programmer’s Model ARM720T CORE CPU MANUAL EPSON 2-7 2.6.3 The relationship between ARM and Thumb state registers The Thumb state registers relate to the ARM state registers in the following ways: • Thumb state r0–r7, and ARM state r0–r7 are identical • Thumb state CPSR and SPSRs, and ARM state C...

Page 48 - Program status registers; Figure 2-6 Program status register format; The condition code flags; The control bits

2: Programmer’s Model 2-8 EPSON ARM720T CORE CPU MANUAL 2.7 Program status registers The ARM720T processor contains a CPSR, and five SPSRs for use by exception handlers. These registers: • hold information about the most recently performed ALU operation • control the enabling and disabling of interr...

Page 49 - Reserved bits; Table 2-2 PSR mode bit values

2: Programmer’s Model ARM720T CORE CPU MANUAL EPSON 2-9 2.7.3 Reserved bits The remaining bits in the PSRs are reserved. When changing flag or control bits of a PSR, you must ensure that these unused bits are not altered. Also, your program must not rely on them containing specific values, because i...

Page 50 - Exceptions; Exception behavior is described in the following sections:; Action on entering an exception; in ARM or Thumb state.

2: Programmer’s Model 2-10 EPSON ARM720T CORE CPU MANUAL 2.8 Exceptions Exceptions arise whenever the normal flow of a program has to be halted temporarily, for example to service an interrupt from a peripheral. Before an exception can be handled, the current processor state is preserved so that the...

Page 51 - Action on leaving an exception; depending on the type of exception.; Exception entry and exit summary; Table 2-3 Exception entry and exit

2: Programmer’s Model ARM720T CORE CPU MANUAL EPSON 2-11 2.8.2 Action on leaving an exception On completion, the exception handler: 1 Moves the LR, minus an offset where appropriate, to the PC. The offset varies depending on the type of exception. 2 Copies the SPSR back to the CPSR. 3 Clears the int...

Page 52 - Fast interrupt request; SWP

2: Programmer’s Model 2-12 EPSON ARM720T CORE CPU MANUAL 2.8.4 Fast interrupt request The FIQ exception is used for most performance-critical interrupts in a system. In ARM state the processor has sufficient private registers to remove the necessity for register saving, minimizing the overhead of co...

Page 53 - for a Prefetch Abort; External aborts; Software interrupt; Control; The low addresses are the defaults.

2: Programmer’s Model ARM720T CORE CPU MANUAL EPSON 2-13 After fixing the reason for the abort, the handler must execute the following irrespective of the processor state (ARM or Thumb): SUBS PC, r14_abt, #4 for a Prefetch Abort SUBS PC, r14_abt, #8 for a Data Abort This restores both the PC and the...

Page 54 - Exception priorities; in which they are handled:; Exception restrictions

2: Programmer’s Model 2-14 EPSON ARM720T CORE CPU MANUAL 2.8.10 Exception priorities When multiple exceptions arise at the same time, a fixed priority system determines the order in which they are handled: 1 Reset (highest priority). 2 Data Abort. 3 FIQ. 4 IRQ. 5 Prefetch Abort. 6 Undefined Instruct...

Page 55 - Relocation of low virtual addresses by the FCSE PID; The ARM720T processor provides a mechanism,; Fast Context Switch Extension; FCSE PID are fetched with a relocation to the previous FCSE PID

2: Programmer’s Model ARM720T CORE CPU MANUAL EPSON 2-15 2.9 Relocation of low virtual addresses by the FCSE PID The ARM720T processor provides a mechanism, Fast Context Switch Extension (FCSE), to translate virtual addresses to physical addresses based on the current value of the FCSE Process IDent...

Page 56 - Reset; Translation Lookaside Buffer

2: Programmer’s Model 2-16 EPSON ARM720T CORE CPU MANUAL 2.10 Reset When the HRESETn signal goes LOW, the ARM720T processor: 1 Abandons the executing instruction. 2 Flushes the cache and Translation Lookaside Buffer (TLB). 3 Disables the Write Buffer (WB), cache, and MMU. 4 Resets the FCSE PID. 5 Co...

Page 57 - Implementation-defined behavior of instructions; Indexed addressing on a Data Abort; Rn; Early termination

2: Programmer’s Model ARM720T CORE CPU MANUAL EPSON 2-17 2.11 Implementation-defined behavior of instructions The ARM Architecture Reference Manual defines the instruction set of the ARM720T processor: • See Indexed addressing on a Data Abort for the behavior of instructions that are identified as i...

Page 61 - About configuration; Compatibility

3: Configuration ARM720T CORE CPU MANUAL EPSON 3-1 3 Configuration This chapter describes the configuration of the ARM720T processor. It contains the following sections. 3.1 About configuration.................................................................................... 3-1 3.2 Internal copro...

Page 62 - Internal coprocessor instructions; a single module, enabling it to be easily updated.

3: Configuration 3-2 EPSON ARM720T CORE CPU MANUAL 3.2 Internal coprocessor instructions The instruction set for the ARM720T processor enables you to implement specialized additional instructions using coprocessors. These are separate processing units that are coupled to the ARM720T processor, altho...

Page 63 - ID Register; Reading from CP15 Register 0 returns the value:

3: Configuration ARM720T CORE CPU MANUAL EPSON 3-3 3.3 Registers The ARM720T processor contains registers that control the cache and MMU operation. You can access these registers using MCR and MRC instructions to CP15 with the processor in a privileged mode. Table 3-1 shows a summary of valid CP15 r...

Page 64 - Figure 3-4 Control Register read format

3: Configuration 3-4 EPSON ARM720T CORE CPU MANUAL 3.3.2 Control Register Reading from CP15 Register 1 reads the control bits. The CRm and opcode_2 fields Should Be Zero when reading CP15 Register 1. Control Register read format is shown in Figure 3-4. Figure 3-4 Control Register read format Writing...

Page 65 - Enabling the MMU; Interaction of the MMU and cache; Translation Table Base Register; Figure 3-6 Translation Table Base Register format

3: Configuration ARM720T CORE CPU MANUAL EPSON 3-5 Bits 12:10 When read, this returns an Unpredictable value. When written, it Should Be Zero, or a value read from these bits on the same processor. Note: Using a read-write-modify sequence when modifying this register provides the greatest future com...

Page 66 - Domain Access Control Register; Figure 3-7 Domain Access Control Register format; Fault Status Register; Figure 3-8 Fault Status Register format

3: Configuration 3-6 EPSON ARM720T CORE CPU MANUAL 3.3.4 Domain Access Control Register Reading from CP15 Register 3 returns the value of the Domain Access Control Register.Writing to CP15 Register 3 writes the value of the Domain Access Control Register.The Domain Access Control Register consists o...

Page 67 - Reading CP15 Register 6 returns the value of the; Fault Address Register; Address Register format is shown in Figure 3-9.; Cache Operations Register; instruction that writes the CP15 Register 7.; TLB Operations Register; Writing to CP15 Register 8 controls the; Table 3-2 Cache operation; Table 3-3 TLB operations

3: Configuration ARM720T CORE CPU MANUAL EPSON 3-7 3.3.6 Fault Address Register Reading CP15 Register 6 returns the value of the Fault Address Register (FAR). The FAR holds the virtual address of the access that was attempted when a fault occurred. The FAR is only updated on data faults. There is no...

Page 68 - Process Identifier Registers; Fast Context Switch Extension Process Identifier Register; Figure 3-10 FCSCE PID Register format; Changing FCSE PID; similarities with a branch with delayed execution. See; Trace Process Identifier Register; A 32-bit read/write register is provided to hold a Trace

3: Configuration 3-8 EPSON ARM720T CORE CPU MANUAL In the instructions shown in Table 3-3, c7 is the preferred value for the CRn field, because it indicates a unified MMU.Reading from CP15 Register 8 is undefined.The Invalidate TLB single entry function invalidates any TLB entry corresponding to the...

Page 69 - Register 14, reserved; Test Support

3: Configuration ARM720T CORE CPU MANUAL EPSON 3-9 3.3.10 Register 14, reserved Accessing this register is undefined. Writing to Register 14 is Undefined. 3.3.11 Test Register The CP15 Register 15 is used for device-specific test operations. For more information, see Chapter 11 Test Support .

Page 73 - About the instruction and data cache; random replacement algorithm.; IDC operation; The ARM720T contains an 8KB mixed; Instruction and Data Cache; Register and is disabled on HRESETn.; Cachable bit; and it is randomly placed in a cache bank.

4: Instruction and Data Cache ARM720T CORE CPU MANUAL EPSON 4-1 4 Instruction and Data Cache This chapter describes the instruction and data cache. It contains the following sections: 4.1 About the instruction and data cache ....................................................... 4-1 4.2 IDC validit...

Page 74 - IDC validity; Software IDC flush

4: Instruction and Data Cache 4-2 EPSON ARM720T CORE CPU MANUAL 4.1.3 Read-lock-write The IDC treats the read-lock-write instruction as a special case: Read phase Always forces a read of external memory, regardless of whether the data is contained in the cache. Write phase Is treated as a normal wri...

Page 75 - Write Buffer

Page 77 - About the write buffer; eight words of data; Bufferable; corresponding page table must be set.; Bufferable bit

5: Write Buffer ARM720T CORE CPU MANUAL EPSON 5-1 5 Write Buffer This chapter describes the write buffer. It contains the following sections: 5.1 About the write buffer................................................................................ 5-1 5.2 Write buffer operation .......................

Page 78 - Write buffer operation; Bufferable write; write, even if it is marked as buffered.; Reading from a noncachable area; processor is stalled.; Draining the write buffer; register 1) before moving large blocks of data.

5: Write Buffer 5-2 EPSON ARM720T CORE CPU MANUAL 5.2 Write buffer operation You control the operation of the write buffer with CP15 register 1, the Control Register (see Control Register on page 3-4). When the CPU performs a write operation, the translation entry for that address is inspected and t...

Page 79 - The Bus Interface

Page 81 - About the bus interface; Advanced High-performance Bus; Summary of the AHB transfer mechanism; This phase can be extended using the; HREADY; time for a slave to provide or sample data.

6: The Bus Interface ARM720T CORE CPU MANUAL EPSON 6-1 6 The Bus Interface This chapter describes the signals on the bus interface of the ARM720T processor. It contains the following sections: 6.1 About the bus interface .............................................................................. ...

Page 82 - Address and control signals

6: The Bus Interface 6-2 EPSON ARM720T CORE CPU MANUAL Figure 6-1 shows a transfer with no wait states (this is the simplest type of transfer). Figure 6-1 Simple AHB transfer A granted bus master starts an AHB transfer by driving the address and control signals. These signals provide the following i...

Page 83 - Bus interface signals

6: The Bus Interface ARM720T CORE CPU MANUAL EPSON 6-3 6.2 Bus interface signals The signals in the ARM720T processor bus interface can be grouped into the following categories: Transfer type HTRANS[1:0]See Transfer types on page 6-5. Address and control HADDR[31:0]HWRITEHSIZE[2:0]HBURST[2:0]HPROT[3...

Page 85 - Transfer types; Figure 6-3 Simple memory cycle

6: The Bus Interface ARM720T CORE CPU MANUAL EPSON 6-5 6.3 Transfer types The ARM720T processor bus interface is pipelined, so the address-class signals and the memory request signals are broadcast in the bus cycle ahead of the bus cycle to which they refer. This gives the maximum time for a memory ...

Page 87 - HWRITE; Indicates an ARM720T processor write cycle.

6: The Bus Interface ARM720T CORE CPU MANUAL EPSON 6-7 6.4 Address and control signals The address and control signals are described in the following sections: • HADDR[31:0] • HWRITE • HSIZE[2:0] • HBURST[2:0] on page 6-8 • HPROT[3:0] on page 6-8. 6.4.1 HADDR[31:0] HADDR[31:0] is the 32-bit address ...

Page 89 - Slave transfer response signals

6: The Bus Interface ARM720T CORE CPU MANUAL EPSON 6-9 6.5 Slave transfer response signals After a master has started a transfer, the slave determines how the transfer progresses. No provision is made in the AHB specification for a bus master to cancel a transfer after it has begun.Whenever a slave ...

Page 90 - For a full description of the slave transfer responses, see the; Data buses; read and write data buses are required.

6: The Bus Interface 6-10 EPSON ARM720T CORE CPU MANUAL 6.5.2 HRESP[1:0] HRESP[1:0] is used by the slave to show the status of a transfer. The HRESP[1:0] encodings are shown in Table 6-5. For a full description of the slave transfer responses, see the AMBA Specification (Rev 2.0) . 6.6 Data buses To...

Page 91 - Endianness; Table 6-6 Active byte lanes for a 32-bit little-endian data bus

6: The Bus Interface ARM720T CORE CPU MANUAL EPSON 6-11 6.6.2 HRDATA[31:0] The read data bus is driven by the appropriate slave during read transfers. If the slave extends the read transfer by holding HREADY LOW, the slave has to provide valid data only at the end of the final cycle of the transfer,...

Page 92 - Arbitration; The arbitration mechanism is described fully in the; HBUSREQ; at the rising edge of HCLK.

6: The Bus Interface 6-12 EPSON ARM720T CORE CPU MANUAL Table 6-7 shows active byte lanes for big-endian systems. 6.7 Arbitration The arbitration mechanism is described fully in the AMBA Specification (Rev 2.0) . This mechanism is used to ensure that only one master has access to the bus at any one ...

Page 93 - Bus clocking; There are two clock inputs on the ARM720T processor bus interface.; timings are related to the rising edge of HCLK.; HCLKEN; by dividing HCLK for the bus interface.; the address and control signals are at valid levels

6: The Bus Interface ARM720T CORE CPU MANUAL EPSON 6-13 6.8 Bus clocking There are two clock inputs on the ARM720T processor bus interface. 6.8.1 HCLK The bus is clocked by the system clock, HCLK. This clock times all bus transfers. All signal timings are related to the rising edge of HCLK. 6.8.2 HC...

Page 97 - About the MMU; Modified Virtual Address

7: Memory Management Unit ARM720T CORE CPU MANUAL EPSON 7-1 7 Memory Management Unit This chapter describes the Memory Management Unit (MMU). It contains the following sections: 7.1 About the MMU.......................................................................................... 7-1 7.2 MMU pr...

Page 98 - Access permissions and domains

7: Memory Management Unit 7-2 EPSON ARM720T CORE CPU MANUAL 7.1.1 Access permissions and domains For large and small pages, access permissions are defined for each subpage (4KB for small pages, 16KB for large pages). Sections and tiny pages have a single set of access permissions. All regions of mem...

Page 99 - MMU program-accessible registers; stored in memory to determine the operation of the MMU.; , with details of register formats and the

7: Memory Management Unit ARM720T CORE CPU MANUAL EPSON 7-3 7.2 MMU program-accessible registers Table 7-1 lists the CP15 registers that are used in conjunction with page table descriptors stored in memory to determine the operation of the MMU. All the CP15 MMU registers, except register c8, contain...

Page 100 - Address translation; large pages; the requested MVA. The; Translation Table Base; register points to the base address of a table

7: Memory Management Unit 7-4 EPSON ARM720T CORE CPU MANUAL 7.3 Address translation The MMU translates VAs generated by the CPU core, and by CP15 register c13, into physical addresses to access external memory. It also derives and checks the access permission, using the TLB.The MMU table walking har...

Page 102 - Figure 7-3 Accessing translation table level one descriptors; Level one descriptor; Figure 7-4 Level one descriptor

7: Memory Management Unit 7-6 EPSON ARM720T CORE CPU MANUAL 7.3.2 Level one fetch Bits [31:14] of the Translation Table Base Register are concatenated with bits [31:20] of the MVA to produce a 30-bit address as shown in Figure 7-3. Figure 7-3 Accessing translation table level one descriptors This ad...

Page 103 - Level one descriptor bit assignments are shown in Table 7-2.

7: Memory Management Unit ARM720T CORE CPU MANUAL EPSON 7-7 Level one descriptor bit assignments are shown in Table 7-2. The two least significant bits of the level one descriptor indicate the descriptor type as shown in Table 7-3. Table 7-2 Level one descriptor bits Bits Description Section Coarse ...

Page 104 - Section descriptor; format of a section descriptor.; Coarse page table descriptor; coarse page table descriptor.

7: Memory Management Unit 7-8 EPSON ARM720T CORE CPU MANUAL 7.3.4 Section descriptor A section descriptor provides the base address of a 1MB block of memory. Figure 7-5 shows the format of a section descriptor. Figure 7-5 Section descriptor Section descriptor bit assignments are described in Table 7...

Page 105 - Fine page table descriptor; format of a fine page table descriptor.

7: Memory Management Unit ARM720T CORE CPU MANUAL EPSON 7-9 Coarse page table descriptor bit assignments are described in Table 7-5. 7.3.6 Fine page table descriptor A fine page table descriptor provides the base address of a page table that contains level two descriptors for large page, small page,...

Page 106 - Translating section references; Figure 7-8 shows the complete section translation sequence.; Level two descriptor; Figure 7-9 Level two descriptor

7: Memory Management Unit 7-10 EPSON ARM720T CORE CPU MANUAL 7.3.7 Translating section references Figure 7-8 shows the complete section translation sequence. Figure 7-8 Section translation Note: You must check access permissions contained in the level one descriptor before generating the physical ...

Page 107 - access permission bits.

7: Memory Management Unit ARM720T CORE CPU MANUAL EPSON 7-11 A level two descriptor defines a tiny, a small, or a large page descriptor, or is invalid: • a large page descriptor provides the base address of a 64KB block of memory • a small page descriptor provides the base address of a 4KB block of ...

Page 108 - Translating large page references; Figure 7-10 Large page translation from a coarse page table

7: Memory Management Unit 7-12 EPSON ARM720T CORE CPU MANUAL 7.3.9 Translating large page references Figure 7-10 shows the complete translation sequence for a 64KB large page. Figure 7-10 Large page translation from a coarse page table Because the upper four bits of the page index and low-order four...

Page 109 - Translating small page references; Figure 7-11 Small page translation from a coarse page table

7: Memory Management Unit ARM720T CORE CPU MANUAL EPSON 7-13 7.3.10 Translating small page references Figure 7-11 shows the complete translation sequence for a 4KB small page. Figure 7-11 Small page translation from a coarse page table If a small page descriptor is included in a fine page table, the...

Page 110 - Translating tiny page references; Figure 7-12 Tiny page translation from a fine page table; Subpages; invalidate all four subpages separately.

7: Memory Management Unit 7-14 EPSON ARM720T CORE CPU MANUAL 7.3.11 Translating tiny page references Figure 7-12 shows the complete translation sequence for a 1KB tiny page. Figure 7-12 Tiny page translation from a fine page table Page translation involves one additional step beyond that of a sectio...

Page 111 - MMU faults and CPU aborts; Fault address and fault status registers

7: Memory Management Unit ARM720T CORE CPU MANUAL EPSON 7-15 7.4 MMU faults and CPU aborts The MMU generates an abort on the following types of faults: • alignment faults (data accesses only) • translation faults • domain faults • permission faults. In addition, an external abort can be raised by th...

Page 112 - encoded in the priority given in Table 7-9.; Fault Status; and details how these are interpreted to generate faults.

7: Memory Management Unit 7-16 EPSON ARM720T CORE CPU MANUAL 7.5 Fault address and fault status registers On an abort, the MMU places an encoded 4-bit value, FS[3:0], along with the 4-bit encoded domain number, in the data FSR, and the MVA associated with the abort is latched into the FAR. If an acc...

Page 113 - Figure 7-13 Domain Access Control Register format

7: Memory Management Unit ARM720T CORE CPU MANUAL EPSON 7-17 7.6 Domain access control MMU accesses are primarily controlled through the use of domains. There are 16 domains and each has a 2-bit field to define access to it. Two types of user are supported, clients and managers. The domains are defi...

Page 114 - Access Permission

7: Memory Management Unit 7-18 EPSON ARM720T CORE CPU MANUAL Table 7-10 shows how to interpret the Access Permission (AP) bits and how their interpretation is dependent on the S and R bits (control register bits 8 and 9). Table 7-11 Interpreting access permission (AP) bits AP S R Supervisorpermissio...

Page 115 - Fault checking sequence; sequence for both types of access is shown in Figure 7-14.; Alignment fault; reference to more permission checks.

7: Memory Management Unit ARM720T CORE CPU MANUAL EPSON 7-19 7.7 Fault checking sequence The sequence the MMU uses to check for access faults is different for sections and pages. The sequence for both types of access is shown in Figure 7-14. Figure 7-14 Sequence for checking faults The conditions th...

Page 116 - Translation fault

7: Memory Management Unit 7-20 EPSON ARM720T CORE CPU MANUAL 7.7.2 Translation fault There are two types of translation fault: Section A section translation fault is generated if the level one descriptor is marked as invalid. This happens if bits [1:0] of the descriptor are both 0. Page A page trans...

Page 117 - Bus Interface Unit; Read control register; Disabling the MMU

7: Memory Management Unit ARM720T CORE CPU MANUAL EPSON 7-21 7.8 External aborts In addition to the MMU-generated aborts, the ARM720T processor can be externally aborted by the AMBA bus. This can be used to flag an error on an external memory access. However, not all accesses can be aborted in this ...

Page 119 - Coprocessor Interface

Page 121 - About coprocessors

8: Coprocessor Interface ARM720T CORE CPU MANUAL EPSON 8-1 8 Coprocessor Interface This chapter describes the coprocessor interface on the ARM720T processor. It contains the following sections: 8.1 About coprocessors ......................................................................................

Page 122 - Coprocessor availability; coprocessor

8: Coprocessor Interface 8-2 EPSON ARM720T CORE CPU MANUAL The coprocessor: 1 Decodes instructions to determine whether it can accept the instruction. 2 Indicates whether it can accept the instruction (by signaling on EXTCPA and EXTCPB). 3 Fetches any values required from its own register bank. 4 Pe...

Page 123 - Coprocessor interface signals

8: Coprocessor Interface ARM720T CORE CPU MANUAL EPSON 8-3 8.2 Coprocessor interface signals The signals used to interface the ARM720T core to a coprocessor are grouped into four categories.The clock and clock control signals include the main processor clock and bus reset: • HCLK • EXTCPCLKEN • HRES...

Page 124 - Pipeline-following signals; all

8: Coprocessor Interface 8-4 EPSON ARM720T CORE CPU MANUAL 8.3 Pipeline-following signals Every coprocessor in the system must contain a pipeline follower to track the instructions executing in the ARM720T processor pipeline. The coprocessors connect to the ARM720T processor input data bus, EXTCPDOU...

Page 125 - Coprocessor interface handshaking; These signals are explained in more detail in; Coprocessor signaling; The coprocessor; The coprocessor attempts to execute the instruction.

8: Coprocessor Interface ARM720T CORE CPU MANUAL EPSON 8-5 8.4 Coprocessor interface handshaking The ARM720T core and any coprocessors in the system perform a handshake using the signals shown in Table 8-2. These signals are explained in more detail in Coprocessor signaling on page 8-6. 8.4.1 The co...

Page 126 - Figure 8-1 Coprocessor busy-wait sequence; Consequences of busy-waiting

8: Coprocessor Interface 8-6 EPSON ARM720T CORE CPU MANUAL 8.4.3 Coprocessor signaling The coprocessor signals as follows: Coprocessor absent If a coprocessor cannot accept the instruction currently in Decode it must leave EXTCPA and EXTCPB both HIGH. Coprocessor present If a coprocessor can accept ...

Page 127 - Coprocessor register transfer instructions; Figure 8-2 Coprocessor register transfer sequence; Coprocessor data operations; Figure 8-3 Coprocessor data operation sequence

8: Coprocessor Interface ARM720T CORE CPU MANUAL EPSON 8-7 8.4.5 Coprocessor register transfer instructions The coprocessor register transfer instructions, MCR and MRC, transfer data between a register in the ARM720T processor register bank and a register in the coprocessor register bank. An example...

Page 128 - Coprocessor load and store operations; The external coprocessor must not abort on

8: Coprocessor Interface 8-8 EPSON ARM720T CORE CPU MANUAL 8.4.7 Coprocessor load and store operations The coprocessor load and store instructions, LDC and STC, are used to transfer data between a coprocessor and memory. They can be used to transfer either a single word of data or a number of the co...

Page 129 - Connecting coprocessors; transfer data from memory (instruction stream and LDC); Connecting a single coprocessor; HIGH by the external coprocessor when it drives data on EXTCPDOUT.; Connecting multiple coprocessors; You must also multiplex the output data from the coprocessors.

8: Coprocessor Interface ARM720T CORE CPU MANUAL EPSON 8-9 8.5 Connecting coprocessors A coprocessor in a system based on an ARM720T processor must have 32-bit connections to: • transfer data from memory (instruction stream and LDC) • write data from the ARM720T processor (MCR) • read data to the AR...

Page 130 - Not using an external coprocessor; UNDEFINED; Privileged instructions; Table 8-4 CPnTRANS signal meanings

8: Coprocessor Interface 8-10 EPSON ARM720T CORE CPU MANUAL 8.6 Not using an external coprocessor If you are implementing a system that does not include any external coprocessors, you must tie both EXTCPA and EXTCPB HIGH. This indicates that no external coprocessors are present in the system. If any...

Page 131 - Debugging Your System

Page 134 - About debugging your system; A typical debug system; Figure 9-1 Typical debug system

9: Debugging Your System 9-2 EPSON ARM720T CORE CPU MANUAL 9.1 About debugging your system The advanced debugging features of the ARM720T processor make it easier to develop application software, operating systems, and the hardware itself. 9.1.1 A typical debug system The ARM720T processor forms one...

Page 135 - Controlling debugging; The; Figure 9-2 ARM720T processor block diagram

9: Debugging Your System ARM720T CORE CPU MANUAL EPSON 9-3 9.2 Controlling debugging The major blocks of the ARM720T processor are: ARM CPU core This has hardware support for debug. EmbeddedICE-RT macrocell A set of registers and comparators that you use to generate debug exceptions (such as breakpo...

Page 136 - Debug modes

9: Debugging Your System 9-4 EPSON ARM720T CORE CPU MANUAL 9.2.1 Debug modes You can perform debugging in either of the following modes: Halt mode When the system is in halt mode, the core enters debug state when it encounters a breakpoint or a watchpoint. In debug state, the core is stopped and iso...

Page 137 - Entry into debug state; an external debug request.

9: Debugging Your System ARM720T CORE CPU MANUAL EPSON 9-5 9.3 Entry into debug state If the system is in halt mode, any of the following types of interrupt force the processor into debug state: • a breakpoint (a given instruction fetch) • a watchpoint (a data access) • an external debug request. No...

Page 138 - Entry into debug state on breakpoint; Abort

9: Debugging Your System 9-6 EPSON ARM720T CORE CPU MANUAL 9.3.1 Entry into debug state on breakpoint The ARM720T processor marks instructions as being breakpointed as they enter the instruction pipeline, but the core does not enter debug state until the instruction reaches the Execute stage. Breakp...

Page 139 - Entry into debug state on debug request; Programming breakpoints; on page; Programming watchpoints; by asserting the DBGRQ pin.; Action of the ARM720T processor in debug state; core is forced to ignore aborts and interrupts.

9: Debugging Your System ARM720T CORE CPU MANUAL EPSON 9-7 9.3.3 Entry into debug state on debug request An ARM720T core in halt mode can be forced into debug state on debug request in either of the following ways: • through EmbeddedICE-RT programming (see Programming breakpoints on page 9-36, and P...

Page 140 - Clocks; Figure 9-4 Clock synchronization

9: Debugging Your System 9-8 EPSON ARM720T CORE CPU MANUAL 9.3.5 Clocks The system and test clocks must be synchronized externally to the processor. The ARM Multi-ICE debug agent directly supports one or more cores within an ASIC design. Synchronizing off-chip debug clocking with the ARM720T process...

Page 141 - Debug interface; Standard Test; Debug interface signals; ARM720T core clock domains

9: Debugging Your System ARM720T CORE CPU MANUAL EPSON 9-9 9.4 Debug interface The ARM720T processor debug interface is based on IEEE Std. 1149.1- 1990, Standard Test Access Port and Boundary-Scan Architecture . Refer to this standard for an explanation of the terms used in this chapter, and for a d...

Page 142 - The EmbeddedICE-RT macrocell; Watchpoint unit registers

9: Debugging Your System 9-10 EPSON ARM720T CORE CPU MANUAL 9.6 The EmbeddedICE-RT macrocell The ARM720T processor EmbeddedICE-RT macrocell module provides integrated on-chip debug support for the ARM720T core. The EmbeddedICE-RT module is connected directly to the core and therefore functions on th...

Page 143 - Disabling EmbeddedICE-RT

9: Debugging Your System ARM720T CORE CPU MANUAL EPSON 9-11 Abort status register This register identifies whether an abort exception entry was caused by a breakpoint, a watchpoint, or a real abort. For more information, see Abort status register on page 9-38. Debug Communications Channel (DCC) The ...

Page 144 - EmbeddedICE-RT register map; Enabling monitor mode; Debug; Table 9-1 Function and mapping of EmbeddedICE-RT registers

9: Debugging Your System 9-12 EPSON ARM720T CORE CPU MANUAL 9.8 EmbeddedICE-RT register map The locations of the EmbeddedICE-RT registers are shown in Table 9-1. 9.9 Monitor mode debugging The ARM720T processor contains logic that enables the debugging of a system without stopping the core entirely....

Page 145 - Restrictions on monitor-mode debugging; Abort status register

9: Debugging Your System ARM720T CORE CPU MANUAL EPSON 9-13 9.9.2 Restrictions on monitor-mode debugging There are several restrictions you must be aware of when the ARM core is configured for monitor-mode debugging: • Breakpoints and watchpoints cannot be data-dependent in monitor mode. No support ...

Page 146 - The debug communications channel; Debug Communication Channel; MCR; Figure 9-6 Domain Access Control Register

9: Debugging Your System 9-14 EPSON ARM720T CORE CPU MANUAL 9.10 The debug communications channel The ARM720T EmbeddedICE-RT macrocell contains a Debug Communication Channel (DCC) for passing information between the target and the host debugger. This is implemented as coprocessor 14.The DCC comprise...

Page 147 - Instructions; Table 9-2 Domain Access Control Register bit assignments

9: Debugging Your System ARM720T CORE CPU MANUAL EPSON 9-15 The Domain Access Control Register bit assignments are shown in Table 9-2. Note: If execution is halted, bit 0 might remain asserted. The debugger can clear it by writing to the Domain Access Control Register.Writing to this register is rar...

Page 148 - Communications through the DCC; Sending a message to the debugger

9: Debugging Your System 9-16 EPSON ARM720T CORE CPU MANUAL 9.10.2 Communications through the DCC Messages can be sent and received through the DCC. Sending a message to the debugger Messages are sent from the processor to the debugger as follows: 1 When the processor wishes to send a message to Emb...

Page 149 - Scan chains and the JTAG interface; Test Access Port; (TAP) controller controls the scan chains. For more details of; Standard Test Access Port and; Scan chain implementation; chain wrapper if required.; Scan chain 1; data bus bits 0 through 31; Scan chain 2 enables access to the EmbeddedICE-RT registers. See; Test data registers

9: Debugging Your System ARM720T CORE CPU MANUAL EPSON 9-17 9.11 Scan chains and the JTAG interface There are three JTAG-style scan chains within the ARM720T processor. These enable debugging and EmbeddedICE-RT programming.A JTAG-style Test Access Port (TAP) controller controls the scan chains. For ...

Page 150 - Controlling the JTAG interface; Instruction register; on page 9-23). The loading of instructions is controlled by the; For more information about the TAP controller, see; The TAP controller; Table 9-3 Instruction encodings for scan chain 15

9: Debugging Your System 9-18 EPSON ARM720T CORE CPU MANUAL Scan chain 15 Scan chain 15 is dedicated to the system control coprocessor registers (the CP15 registers).There are 37 bits in scan chain 15. From DBGTDI to DBGTDO, the order of the bits is: • read/write bit • instruction encoding bits [3:0...

Page 151 - Figure 9-8 Test access port controller state transitions; Resetting the TAP controller; to the DBGnTRST signal:

9: Debugging Your System ARM720T CORE CPU MANUAL EPSON 9-19 9.12 The TAP controller The TAP controller is a state machine that determines the state of the boundary-scan test signals DBGTDI and DBGTDO. Figure 9-8 shows the state transitions that occur in the TAP controller. Figure 9-8 Test access por...

Page 152 - Public JTAG instructions; Table 9-4 shows the public JTAG instructions.

9: Debugging Your System 9-20 EPSON ARM720T CORE CPU MANUAL 9.13 Public JTAG instructions Table 9-4 shows the public JTAG instructions. In the following descriptions, the ARM720T processor samples DBGTDI and DBGTMS on the rising edge of HCLK with DBGTCKEN HIGH. The TAP controller states are shown in...

Page 153 - ARM720T processor device identification (ID) code register

9: Debugging Your System ARM720T CORE CPU MANUAL EPSON 9-21 9.13.3 IDCODE (b1110) The IDCODE instruction connects the device identification code register (or ID register) between DBGTDI and DBGTDO. The ID register is a 32-bit register that enables the manufacturer, part number, and version of a comp...

Page 154 - Bypass register; Figure 9-9 ID code register format

9: Debugging Your System 9-22 EPSON ARM720T CORE CPU MANUAL 9.14 Test data registers The six test data registers that can connect between DBGTDI and DBGTDO are described in the following sections: • Bypass register • ARM720T processor device identification (ID) code register • Instruction register o...

Page 155 - Table 9-5 Scan chain number allocation

9: Debugging Your System ARM720T CORE CPU MANUAL EPSON 9-23 9.14.3 Instruction register Purpose Changes the current TAP instruction. Length 4 bits. Operating mode In the SHIFT-IR state, the instruction register is selected as the serial path between DBGTDI, and DBGTDO.During the CAPTURE-IR state, th...

Page 156 - Scan chains 1 and 2; System speed access

9: Debugging Your System 9-24 EPSON ARM720T CORE CPU MANUAL 9.14.5 Scan chains 1 and 2 The scan chains enable serial access to the core logic, and to the EmbeddedICE-RT hardware for programming purposes. Each scan chain cell is simple and comprises a serial register and a multiplexor. The scan cells...

Page 157 - Scan timing; Figure 9-10 provides general scan timing information.; Scan chain 1 cells; Table 9-6 Scan chain 1 cells

9: Debugging Your System ARM720T CORE CPU MANUAL EPSON 9-25 During SHIFT-DR, a data value is shifted into the serial register. Bits 32 to 36 specify the address of the EmbeddedICE-RT register to be accessed. During UPDATE-DR, this register is either read or written depending on the value of bit 37 (...

Page 158 - Examining the core and the system in debug state; Bit 4 HIGH

9: Debugging Your System 9-26 EPSON ARM720T CORE CPU MANUAL 9.16 Examining the core and the system in debug state When the ARM720T processor is in debug state, you can examine the core and system state by forcing the load and store multiples into the instruction pipeline.Before you can examine the c...

Page 159 - Determining the core state; when shifting scan chain 1. For example, the encoding for BX R0 is

9: Debugging Your System ARM720T CORE CPU MANUAL EPSON 9-27 9.16.1 Determining the core state When the processor has entered debug state from Thumb state, the simplest course of action is for the debugger to force the core back into ARM state. The debugger can then execute the same sequence of instr...

Page 160 - Determining system state; Debug status register

9: Debugging Your System 9-28 EPSON ARM720T CORE CPU MANUAL All these instructions execute at debug speed. Debug speed is much slower than system speed. This is because between each core clock, 33 clocks occur in order to shift in an instruction, or shift out data. Executing instructions this slowly...

Page 161 - Exit from debug state; The program counter during debug; Figure 9-11 Debug exit sequence

9: Debugging Your System ARM720T CORE CPU MANUAL EPSON 9-29 When the ARM720T processor returns to debug state after a system speed access, bit 33 of scan chain 1 is set HIGH. The state of bit 33 gives the debugger information about why the core entered debug state the first time this scan chain is r...

Page 162 - flow can be interrupted by any of the following:; Breakpoints; remainder of scan chain 1:; Watchpoints; same way as the procedure described in

9: Debugging Your System 9-30 EPSON ARM720T CORE CPU MANUAL Figure 9-3 on page 9-5 shows that the final memory access occurs in the cycle after DBGACK goes HIGH. This is the point at which the cycle counter must be disabled. Figure 9-11 on page 9-29 shows that the first memory access that the cycle ...

Page 163 - Watchpoint with another exception; sequence to return to program execution.; Debug request; execution straight away. You could use the following sequence:

9: Debugging Your System ARM720T CORE CPU MANUAL EPSON 9-31 9.18.3 Watchpoint with another exception If a watchpointed access simultaneously causes a Data Abort, the ARM720T processor enters debug state in abort mode. Entry into debug is held off until the core changes into abort mode and has fetche...

Page 164 - Summary of return address calculations; Priorities and exceptions; Breakpoint with Prefetch Abort; Table 9-7 Determining the cause of entry to debug state

9: Debugging Your System 9-32 EPSON ARM720T CORE CPU MANUAL 9.18.6 Summary of return address calculations To determine whether entry to debug state was due to a breakpoint, watchpoint, or debug request (DBGRQ), bit 33 (DBGBREAK) of scan chain 1 must be consulted together with bit 12 (DBGMOE) of the ...

Page 165 - Interrupts; watchpoint 0; Programming and reading watchpoint registers

9: Debugging Your System ARM720T CORE CPU MANUAL EPSON 9-33 9.19.2 Interrupts When the ARM720T processor enters debug state, interrupts are automatically disabled.If an interrupt is pending during the instruction prior to entering debug state, the ARM720T processor enters debug state in the mode of ...

Page 167 - Using the data, and address mask registers; xffffffff; The watchpoint unit control registers; Figure 9-13 Watchpoint control value, and mask format

9: Debugging Your System ARM720T CORE CPU MANUAL EPSON 9-35 9.20.2 Using the data, and address mask registers For each value register in a register pair, there is a mask register of the same format. Setting a bit to 1 in the mask register has the effect of making the corresponding bit in the value r...

Page 168 - Hardware breakpoints

9: Debugging Your System 9-36 EPSON ARM720T CORE CPU MANUAL DBGEXT[1:0] Is an external input to EmbeddedICE-RT logic that enables the watchpoint to be dependent on some external condition. The DBGEXT input for Watchpoint 0 is labeled DBGEXT[0].The DBGEXT input for Watchpoint 1 is labeled DBGEXT[1]. ...

Page 169 - Software breakpoints; xFFFFFFFF; Setting the breakpoint

9: Debugging Your System ARM720T CORE CPU MANUAL EPSON 9-37 3 Program the data value register only when you require a data-dependent breakpoint, that is only when you have to match the actual instruction code fetched as well as the address. If the data value is not required, program the data mask re...

Page 170 - Figure 9-14 Debug abort status register

9: Debugging Your System 9-38 EPSON ARM720T CORE CPU MANUAL 9.22 Programming watchpoints This section contains examples of how to program the watchpoint unit to generate breakpoints and watchpoints. Many other ways of programming the watchpoint unit registers are possible. For example, simple range ...

Page 171 - watchpoint unit register is read. See; on page 9-33 for more

9: Debugging Your System ARM720T CORE CPU MANUAL EPSON 9-39 9.24 Debug control register The Debug Control Register is six bits wide. Writes to the Debug Control Register occur when a watchpoint unit register is written. Reads of the Debug Control Register occur when a watchpoint unit register is rea...

Page 172 - Disabling interrupts; IRQs and FIQs are disabled under the following conditions:; Forcing DBGRQ; Table 9-10 Interrupt signal control

9: Debugging Your System 9-40 EPSON ARM720T CORE CPU MANUAL 9.24.1 Disabling interrupts IRQs and FIQs are disabled under the following conditions: • during debugging (DBGACK HIGH) • when the INTDIS bit is set. The core interrupt enable signal, IFEN, is driven as shown in Table 9-10. 9.24.2 Forcing D...

Page 173 - Figure 9-16 Debug status register format

9: Debugging Your System ARM720T CORE CPU MANUAL EPSON 9-41 9.25 Debug status register The debug status register is 13 bits wide. If it is accessed for a write (with the read/write bit set), the status bits are written. If it is accessed for a read (with the read/write bit clear), the status bits ar...

Page 175 - Coupling breakpoints and watchpoints; Breakpoint and watchpoint coupling example; CHAINOUT signal

9: Debugging Your System ARM720T CORE CPU MANUAL EPSON 9-43 9.26 Coupling breakpoints and watchpoints You can couple watchpoint units 1 and 0 together using the CHAIN and RANGE inputs. The use of CHAIN enables Watchpoint 0 to be triggered only if Watchpoint 1 has previously matched. The use of RANGE...

Page 176 - DBGRNG signal; EmbeddedICE-RT timing

9: Debugging Your System 9-44 EPSON ARM720T CORE CPU MANUAL 9.26.2 DBGRNG signal The DBGRNG signal is derived as follows: DBGRNG = ((({Av[31:0],Cv[4:0]} XNOR {A[31:0],C[4:0]}) OR {Am[31:0],Cm[4:0]}) == 0xFFFFFFFFF) AND ((({Dv[31:0],Cv[7:5]} XNOR {D[31:0],C[7:5]}) OR Dm[31:0],Cm[7:5]}) == 0x7FFFFFFFF...

Page 177 - ETM Interface

Page 179 - About the ETM interface; Embedded Trace Macrocell; Enabling and disabling the ETM7 interface; Embedded Trace Macrocell Specification

10: ETM Interface ARM720T CORE CPU MANUAL EPSON 10-1 10 ETM Interface This chapter describes the ETM interface that is provided on the ARM720T processor. It contains the following sections: 10.1 About the ETM interface ......................................................................... 10-1 10...

Page 181 - ETM7 Technical Reference; Debug request wiring; TAP interface wiring; TAP interface wiring

10: ETM Interface ARM720T CORE CPU MANUAL EPSON 10-3 10.4 Clocks and resets The ARM720T processor uses a single clock, HCLK, as both the main system clock and the JTAG clock. You must connect the processor clock to both HCLK and TCK on the ETM. You can then use TCKEN to control the JTAG interface.To...

Page 185 - About the ARM720T test registers; operations. You can use it to access and control the following:; Test State Register; You must only use these operations for test. The; Figure 11-1 CP15 MRC and MCR bit pattern

11: Test Support ARM720T CORE CPU MANUAL EPSON 11-1 11 Test Support This chapter describes the test methodology and the CP15 test registers for the ARM720T processor synthesized logic and TCM. It contains the following sections: 11.1 About the ARM720T test registers.....................................

Page 186 - Automatic Test Pattern Generation; (ATPG) tools to create the necessary scan patterns to test; ARM720T processor INTEST/EXTEST wrapper; ATPG; Table 11-1 Summary of ATPG test signals

11: Test Support 11-2 EPSON ARM720T CORE CPU MANUAL 11.2 Automatic Test Pattern Generation (ATPG) Scan insertion is already performed and fixed for the ARM720T processor. You can use Automatic Test Pattern Generation (ATPG) tools to create the necessary scan patterns to test the logic outputs from a...

Page 187 - Table 11-2 Test State Register operations

11: Test Support ARM720T CORE CPU MANUAL EPSON 11-3 11.3 Test State Register The test state register contains only one bit, bit 0: Bit 0 set Enable MMU and cache test. Bit 0 clear Disable MMU and cache test. At reset (HRESETn LOW), bit 0 is cleared.The test state register operations are shown in Tab...

Page 190 - Addressing the CAM and RAM; and lockdown operations are shown in Table 11-4.

11: Test Support 11-6 EPSON ARM720T CORE CPU MANUAL The CAM match, RAM read format for data is shown in Figure 11-9. Figure 11-9 Data format, CAM match RAM read 11.4.1 Addressing the CAM and RAM For the CAM read or write, and RAM read or write operations you must specify the segment, index, and word...

Page 192 - MMU test registers and operations

11: Test Support 11-8 EPSON ARM720T CORE CPU MANUAL ; Now read and check MOV r8,#8MOV r2,#0x10MOV r1,#0 loop1 MCR p15,3,r1,c15,c3,0 ; write C15.C to ‘0’ MCR p15,2,r2,c15,c11,2 ; read RAM to C15.C MRC p15,3,r5,c15,c3,0 ; read C15.C to R4 ADD r2,r2,#0x04CMP r5,r0BNE TEST_FAILSUBS r8,r8,#1BNE loop1B TE...

Page 201 - AMBA interface signals; The AMBA interface signals are shown in Table A-1.

A: Signal Descriptions ARM720T CORE CPU MANUAL EPSON A-1 A Signal Descriptions This chapter describes the interface signals of the ARM720T processor. It contains the following sections: A.1 AMBA interface signals ............................................................................. A-1 A.2 C...

Page 202 - The coprocessor interface signals are shown in Table A-2.

A: Signal Descriptions A-2 EPSON ARM720T CORE CPU MANUAL A.2 Coprocessor interface signals The coprocessor interface signals are shown in Table A-2. Table A-2 Coprocessor interface signal descriptions Name Type Description EXTCPA Input External coprocessor absent.This signal must be HIGH if no exter...

Page 203 - JTAG and test signals; JTAG and test signal descriptions are shown in Table A-3.

A: Signal Descriptions ARM720T CORE CPU MANUAL EPSON A-3 A.3 JTAG and test signals JTAG and test signal descriptions are shown in Table A-3. Table A-3 JTAG and test signal descriptions Name Type Description DBGIR[3:0] Output TAP instruction register.These signals reflect the current instruction load...

Page 204 - Debugger signals; The debugger signal descriptions are shown in Table A-4.; Table A-4 Debugger signal descriptions

A: Signal Descriptions A-4 EPSON ARM720T CORE CPU MANUAL A.4 Debugger signals The debugger signal descriptions are shown in Table A-4. DBGTDO Output Test data out.JTAG test data out signal. DBGTMS Input Test mode select.JTAG test mode select signal. a. These signals are only active when scan chain 0...

Page 205 - Embedded trace macrocell interface signals; The ETM interface signals are shown in Table A-5.

A: Signal Descriptions ARM720T CORE CPU MANUAL EPSON A-5 A.5 Embedded trace macrocell interface signals The ETM interface signals are shown in Table A-5. DBGRNG[1:0] Output Range out.These signals indicate that the relevant EmbeddedICE-RT watchpoint register has matched the conditions currently pres...

Page 207 - ATPG test signals; Table A-6 ATPG test signal descriptions

A: Signal Descriptions ARM720T CORE CPU MANUAL EPSON A-7 A.6 ATPG test signals ATPG test signals used by the ARM720T processor are shown in Table A-6. A.7 Miscellaneous signals Miscellaneous signals used by the ARM720T processor are shown in Table A-7. Table A-6 ATPG test signal descriptions Name Ty...

Page 216 - Unpredictable; See also

Glossary Glossary-6 EPSON ARM720T CORE CPU MANUAL Test Access Port The collection of four mandatory and one optional terminals that form the input/output and control interface to a JTAG boundary-scan architecture. The mandatory terminals are TDI, TDO, TMS, and TCK. The optional terminal is nTRST. Th...

Page 217 - Index

Page 219 - at the end. The references given are to page numbers.

Index ARM DDI 0229B EPSON Index-1 Index The items in this index are listed in alphabetical order, with symbols and numerics appearing at the end. The references given are to page numbers. A Abort Data 9-6, 9-31handler 9-6mode 2-4Prefetch 9-32vector 9-31 Abort status register 9-38Aborted watchpoint 9...

Page 223 - International Sales Operations; AMERICA

International Sales Operations AMERICA EPSON ELECTRONICS AMERICA, INC.- HEADQUARTERS - 150 River Oaks ParkwaySan Jose, CA 95134, U.S.A.Phone: +1-408-922-0200 Fax: +1-408-922-0238 - SALES OFFICES -West 1960 E. Grand AvenueEI Segundo, CA 90245, U.S.A.Phone: +1-310-955-5300 Fax: +1-310-955-5400 Central...

Page 224 - CORE CPU MANUAL

ARM720T Revision 4 (AMBA AHB Bus Interface Version) CORE CPU MANUAL EPSON Electronic Devices Website ELECTRONIC DEVICES MARKETING DIVISION http://www.epsondevice.com Issue April, 2004 Printed in Japan C A Document code: 405003400 CORE CPU MANUAL ARM720T Revision 4 (AMBA AHB Bus Interface Version) CO...

Epson ARM720T - Manual

Table of Contents:

Summary

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