Cypress STK14C88-5 - Manual
Cypress STK14C88-5 – Manual, read for free online in PDF format. We hope this helps you resolve any issues you may have. If you have further questions, please contact us through the contact form.
Table of Contents:
- Page 3 – Figure 3; AutoStore Inhibit mode; Figure 4; Figure 3. AutoStore Mode
- Page 4 – Figure 4. AutoStore Inhibit Mode
- Page 5 – STORE; Low Average Active Power; Figure 5; Preventing Store
- Page 6 – Best Practices
- Page 7 – DC Electrical Characteristics
- Page 8 – Capacitance; Thermal Resistance; AC Test Conditions; Output
- Page 9 – AC Switching Characteristics; SRAM Read Cycle; Switching Waveforms
- Page 10 – SRAM Write Cycle
- Page 13 – Hardware STORE Cycle
- Page 14 – Ordering Information; Military; Part Numbering Nomenclature; Retention / Endurance
- Page 15 – Package Diagram
- Page 17 – Document History Page; Worldwide Sales and Design Support; Rev
STK14C88-5
256 Kbit (32K x 8) AutoStore nvSRAM
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document Number: 001-51038 Rev. **
Revised March 02, 2009
Features
■
35 ns and 45 ns access times
■
Hands off automatic STORE on power down with external 68
µF capacitor
■
STORE to QuantumTrap™ nonvolatile elements is initiated by
software, hardware, or AutoStore™ on power down
■
RECALL to SRAM initiated by software or power up
■
Unlimited READ, WRITE, and RECALL cycles
■
1,000,000 STORE cycles to QuantumTrap
■
100 year data retention to QuantumTrap
■
Single 5V+10% operation
■
Military temperature
■
32-pin (300 mil) CDIP and LCC (450 mil) packages
Functional Description
The Cypress STK14C88-5 is a fast static RAM with a nonvolatile
element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
unlimited read and write cycles, while independent, nonvolatile
data resides in the highly reliable QuantumTrap cell. Data
transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down. On
power up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. Both the STORE and RECALL
operations are also available under software control. A hardware
STORE is initiated with the HSB pin.
STORE/
RECALL
CONTROL
POWER
CONTROL
SOFTWARE
DETECT
STATIC RAM
ARRAY
512 X 512
Quantum Trap
512 X 512
STORE
RECALL
COLUMN I/O
COLUMN DEC
ROW DECODER
INPUT
BUFFERS
OE
CE
WE
HSB
V
CC
V
CAP
A
13
-
A
0
A
0
A
1
A
2
A
3
A
4
A
10
A
5
A
6
A
7
A
8
A
9
A
11
A
12
A
13
A
14
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
Logic Block Diagram
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Summary
STK14C88-5 Document Number: 001-51038 Rev. ** Page 3 of 17 Device Operation The STK14C88-5 nvSRAM is made up of two functional compo-nents paired in the same physical cell. These are an SRAMmemory cell and a nonvolatile QuantumTrap cell. The SRAMmemory cell operates as a standard fast static RAM. Da...
STK14C88-5 Document Number: 001-51038 Rev. ** Page 4 of 17 Hardware STORE (HSB) Operation The STK14C88-5 provides the HSB pin for controlling andacknowledging the STORE operations. The HSB pin is used torequest a hardware STORE cycle. When the HSB pin is drivenLOW, the STK14C88-5 conditionally initi...
STK14C88-5 Document Number: 001-51038 Rev. ** Page 5 of 17 Data Protection The STK14C88-5 protects data from corruption during lowvoltage conditions by inhibiting all externally initiated STOREand WRITE operations. The low voltage condition is detectedwhen V CC is less than V SWITCH . If the STK14C8...
