Cypress STK14C88-3 - Manual
Cypress STK14C88-3 – Manual, read for free online in PDF format. We hope this helps you resolve any issues you may have. If you have further questions, please contact us through the contact form.
Table of Contents:
- Page 2 – Pin Configurations
- Page 3 – Figure 2. AutoStore Mode
- Page 4 – Software STORE; Figure 3. AutoStore Inhibit Mode
- Page 5 – STORE; Noise Considerations; Figure 4
- Page 6 – Best Practices
- Page 7 – DC Electrical Characteristics
- Page 8 – Thermal Resistance; AC Test Conditions
- Page 9 – AC Switching Characteristics; SRAM Read Cycle; Switching Waveforms
- Page 13 – Hardware STORE Cycle
- Page 14 – Ordering Information; Commercial; Part Numbering Nomenclature; Lead Finish
- Page 15 – Package Diagrams; PIN 1 ID; REFERENCE JEDEC MO-119
- Page 17 – Worldwide Sales and Design Support; Change
STK14C88-3
256 Kbit (32K x 8) AutoStore nvSRAM
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document Number: 001-50592 Rev. **
Revised January 29, 2009
Features
■
35 ns and 45 ns access times
■
Automatic nonvolatile STORE on power loss
■
Nonvolatile STORE under Hardware or Software control
■
Automatic RECALL to SRAM on power up
■
Unlimited Read/Write endurance
■
Unlimited RECALL cycles
■
1,000,000 STORE cycles
■
100 year data retention
■
Single 3.3V+0.3V power supply
■
Commercial and Industrial Temperatures
■
32-pin (300mil) SOIC and 32-pin (600 mil) PDIP packages
■
RoHS compliance
Functional Description
The Cypress STK14C88-3 is a 256 Kb fast static RAM with
a nonvolatile element in each memory cell. The embedded
nonvolatile elements incorporate QuantumTrap
™
technology producing the world’s most reliable nonvolatile
memory. The SRAM provides unlimited read and write
cycles, while independent, nonvolatile data resides in the
highly reliable QuantumTrap cell. Data transfers from the
SRAM to the nonvolatile elements (the STORE operation)
takes place automatically at power down. On power up, data
is restored to the SRAM (the RECALL operation) from the
nonvolatile memory. Both the STORE and RECALL opera-
tions are also available under software control.
STORE/
RECALL
CONTROL
POWER
CONTROL
SOFTWARE
DETECT
STATIC RAM
ARRAY
512 X 512
Quantum Trap
512 X 512
STORE
RECALL
COLUMN I/O
COLUMN DEC
ROW DECODER
INPUT
BUFFERS
OE
CE
WE
HSB
V
CC
V
CAP
A
13
-
A
0
A
0
A
1
A
2
A
3
A
4
A
10
A
5
A
6
A
7
A
8
A
9
A
11
A
12
A
13
A
14
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
Logic Block Diagram
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Summary
STK14C88-3 Document Number: 001-50592 Rev. ** Page 2 of 17 Pin Configurations Figure 1. Pin Diagram - 32-Pin SOIC/32-Pin PDIP Table 1. Pin Definitions - 32-Pin SOIC/32-Pin PDIP Pin Name Alt IO Type Description A 0 –A 14 Input Address Inputs. Used to select one of the 32,768 bytes of the nvSRAM. DQ 0...
STK14C88-3 Document Number: 001-50592 Rev. ** Page 3 of 17 Device Operation The STK14C88-3 nvSRAM is made up of two functional compo-nents paired in the same physical cell. These are an SRAMmemory cell and a nonvolatile QuantumTrap cell. The SRAMmemory cell operates as a standard fast static RAM. Da...
STK14C88-3 Document Number: 001-50592 Rev. ** Page 4 of 17 Hardware STORE (HSB) Operation The STK14C88-3 provides the HSB pin for controlling andacknowledging the STORE operations. The HSB pin is usedto request a hardware STORE cycle. When the HSB pin isdriven LOW, the STK14C88-3 conditionally initi...
