Cypress STK12C68-5 - Manual
Cypress STK12C68-5 – Manual, read for free online in PDF format. We hope this helps you resolve any issues you may have. If you have further questions, please contact us through the contact form.
Table of Contents:
- Page 3 – Figure 3; Figure 3. AutoStore Mode
- Page 4 – Figure 4. AutoStore Inhibit Mode; AutoStore Inhibit Mode; Figure 4; Software STORE
- Page 5 – Figure 5; Preventing Store
- Page 6 – Best Practices
- Page 7 – DC Electrical Characteristics
- Page 8 – Thermal Resistance; AC Test Conditions
- Page 9 – AC Switching Characteristics; SRAM Read Cycle; Switching Waveforms
- Page 10 – SRAM Write Cycle
- Page 14 – Part Numbering Nomenclature; Retention / Endurance
- Page 15 – Ordering Information; Ordering Code; Military
- Page 16 – Package Diagrams
- Page 18 – Document History Page; Worldwide Sales and Design Support; Rev
STK12C68-5 (SMD5962-94599)
64 Kbit (8K x 8) AutoStore nvSRAM
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document Number: 001-51026 Rev. **
Revised March 02, 2009
Features
■
35 ns and 55 ns access times
■
Hands off automatic STORE on power down with external
68 µF capacitor
■
STORE to QuantumTrap™ nonvolatile elements is initiated
by software, hardware, or AutoStore™ on power down
■
RECALL to SRAM initiated by software or power up
■
Unlimited Read, Write, and Recall cycles
■
1,000,000 STORE cycles to QuantumTrap
■
100 year data retention to QuantumTrap
■
Single 5V+10% operation
■
Military temperature
■
28-pin (300mil) CDIP and 28-pad LCC packages
Functional Description
The Cypress STK12C68-5 is a fast static RAM with a nonvol-
atile element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
unlimited read and write cycles, while independent nonvolatile
data resides in the highly reliable QuantumTrap cell. Data
transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down.
On power up, data is restored to the SRAM (the RECALL
operation) from the nonvolatile memory. Both the STORE and
RECALL operations are also available under software control.
A hardware STORE is initiated with the HSB pin.
Logic Block Diagram
STORE/
RECALL
CONTROL
POWER
CONTROL
SOFTWARE
DETECT
STATIC RAM
ARRAY
128 X 512
Quantum Trap
128 X 512
STORE
RECALL
COLUMN I/O
COLUMN DEC
ROW DECODER
INPUT
BUFFERS
OE
CE
WE
HSB
V
CC
V
CAP
A
0
-
A
12
A
0
A
1
A
2
A
3
A
4
A
10
A
5
A
6
A
7
A
8
A
9
A
11
A
12
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
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Summary
STK12C68-5 (SMD5962-94599) Document Number: 001-51026 Rev. ** Page 3 of 18 Device Operation The STK12C68-5 nvSRAM is made up of two functional compo-nents paired in the same physical cell. These are an SRAMmemory cell and a nonvolatile QuantumTrap cell. The SRAMmemory cell operates as a standard fas...
STK12C68-5 (SMD5962-94599) Document Number: 001-51026 Rev. ** Page 4 of 18 Figure 4. AutoStore Inhibit Mode If the power supply drops faster than 20 us/volt before Vccreaches V SWITCH , then a 2.2 ohm resistor must be connected between V CC and the system supply to avoid momentary excess of current ...
STK12C68-5 (SMD5962-94599) Document Number: 001-51026 Rev. ** Page 5 of 18 4. Read address 0x1FFF, Valid READ 5. Read address 0x10F0, Valid READ 6. Read address 0x0F0E, Initiate RECALL cycle Internally, RECALL is a two step procedure. First, the SRAM datais cleared; then, the nonvolatile information...
