Cypress STK11C68 - Manual
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Table of Contents:
- Page 3 – Figure 2
- Page 4 – Best Practices
- Page 5 – DC Electrical Characteristics
- Page 6 – Capacitance; Thermal Resistance; AC Test Conditions
- Page 7 – AC Switching Characteristics; SRAM Read Cycle; Switching Waveforms
- Page 8 – SRAM Write Cycle
- Page 9 – AutoStore INHIBIT or Power Up RECALL; Power up RECALL Duration; Switching Waveform
- Page 11 – Ordering Information; Ordering Code; Commercial; Part Numbering Nomenclature; Lead Finish
- Page 13 – Package Diagrams
- Page 16 – Document History Page; Worldwide Sales and Design Support; Change
STK11C68
64 Kbit (8K x 8) SoftStore nvSRAM
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document Number: 001-50638 Rev. **
Revised January 30, 2009
Features
■
25 ns, 35 ns, and 45 ns access times
■
Pin compatible with industry standard SRAMs
■
Software initiated nonvolatile STORE
■
Unlimited Read and Write endurance
■
Automatic RECALL to SRAM on power up
■
Unlimited RECALL cycles
■
1,000,000 STORE cycles
■
100 year data retention
■
Single 5V+10% operation
■
Commercial and industrial temperature
■
28-pin (330 mil) SOIC package
■
28-pin (300 mil) CDIP and 28-pad (350 mil) LCC packages
■
RoHS compliance
Functional Description
The Cypress STK11C68 is a 64Kb fast static RAM with a nonvol-
atile element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
unlimited read and write cycles, while independent nonvolatile
data resides in the highly reliable QuantumTrap cell. Data
transfers under software control from SRAM to the nonvolatile
elements (the STORE operation). On power up, data is automat-
ically restored to the SRAM (the RECALL operation) from the
nonvolatile memory. RECALL operations are also available
under software control.
STORE/
RECALL
CONTROL
POWER
CONTROL
SOFTWARE
DETECT
STATIC RAM
ARRAY
128 X 512
Quantum Trap
128 X 512
STORE
RECALL
COLUMN I/O
COLUMN DEC
ROW DECODER
INPUT
BUFFERS
OE
CE
WE
HSB
V
CC
V
CAP
A
0
-
A
12
A
0
A
1
A
2
A
3
A
4
A
10
A
5
A
6
A
7
A
8
A
9
A
11
A
12
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
Logic Block Diagram
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Summary
STK11C68 Document Number: 001-50638 Rev. ** Page 3 of 16 Device Operation The STK11C68 is a versatile memory chip that provides severalmodes of operation. The STK16C88 can operate as a standard8K x 8 SRAM. A 8K x 8 array of nonvolatile storage elements shadow the SRAM. SRAM data can be copied nonvol...
STK11C68 Document Number: 001-50638 Rev. ** Page 4 of 16 average current drawn by the STK11C68 depends on thefollowing items: ■ The duty cycle of chip enable ■ The overall cycle rate for accesses ■ The ratio of Reads to Writes ■ CMOS versus TTL input levels ■ The operating temperature ■ The V CC lev...
STK11C68 Document Number: 001-50638 Rev. ** Page 5 of 16 Maximum Ratings Exceeding maximum ratings may shorten the useful life of thedevice. These user guidelines are not tested. Storage Temperature ................................. –65 ° C to +150 ° C Temperature under bias............................
