Cypress CYDC064B08 - Manual
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Table of Contents:
- Page 2 – Figure 1. Top Level Block Diagram
- Page 3 – Pin Configurations
- Page 5 – Functional Description; Table 1; Pin Definitions
- Page 6 – Table 3; Output Drive Register; Table 4; Semaphore Operation; Table 5
- Page 7 – Architecture
- Page 9 – Electrical Characteristics for V; CC
- Page 10 – Parameter
- Page 13 – Write Cycle; GND
- Page 14 – Switching Characteristics for V
- Page 18 – Switching Waveforms
- Page 23 – Interrupt Timing Diagrams; Right Side Clears INT
- Page 24 – Ordering Information
- Page 25 – Package Diagram
- Page 26 – Document History Page; x 8 ConsuMoBL Dual-Port Static RAM
1.8V 4k/8k/16k x 16 and 8k/16k x 8
ConsuMoBL Dual-Port Static RAM
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 001-01638 Rev. *E
Revised January 25, 2007
Features
• True dual-ported memory cells which allow simulta-
neous access of the same memory location
• 4/8/16k × 16 and 8/16k × 8 organization
• High-speed access: 40 ns
• Ultra Low operating power
— Active: I
CC
= 15 mA (typical) at 55 ns
— Active: I
CC
= 25 mA (typical) at 40 ns
— Standby: I
SB3
= 2
µ
A (typical)
• Port-independent 1.8V, 2.5V, and 3.0V I/Os
• Lead (Pb)-free 14 x 14 x 1.4 mm 100-pin TQFP Package
• Full asynchronous operation
• Pin select for Master or Slave
• Expandable data bus to 32 bits with Master/Slave chip
select when using more than one device
• On-chip arbitration logic
• On-chip semaphore logic
• Input Read Registers and Output Drive Registers
• INT flag for port-to-port communication
• Separate upper-byte and lower-byte control
• Commercial and industrial temperature ranges
Selection Guide for V
CC
= 1.8V
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
-40
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
-55
Unit
Port I/O Voltages (P1-P2)
1.8V-1.8V
1.8V-1.8V
Maximum Access Time
40
55
ns
Typical Operating Current
25
15
mA
Typical Standby Current for I
SB1
2
2
µ
A
Typical Standby Current for I
SB3
2
2
µ
A
Selection Guide for V
CC
= 2.5V
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
-40
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
-55
Unit
Port I/O Voltages (P1-P2)
2.5V-2.5V
2.5V-2.5V
Maximum Access Time
40
55
ns
Typical Operating Current
39
28
mA
Typical Standby Current for I
SB1
6
6
µ
A
Typical Standby Current for I
SB3
4
4
µ
A
Selection Guide for V
CC
= 3.0V
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
-40
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
-55
Unit
Port I/O Voltages (P1-P2)
3.0V-3.0V
3.0V-3.0V
Maximum Access Time
40
55
ns
Typical Operating Current
49
42
mA
Typical Standby Current for I
SB1
7
7
µ
A
Typical Standby Current for I
SB3
6
6
µ
A
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Summary
CYDC256B16, CYDC128B16,CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev. *E Page 2 of 26 Notes: 1. A 0 –A 11 for 4k devices; A 0 –A 12 for 8k devices; A 0 –A 13 for 16k devices. 2. BUSY is an output in master mode and an input in slave mode. IO Control Address Decode Mailboxes INT L INT ...
CYDC256B16, CYDC128B16,CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev. *E Page 3 of 26 Pin Configurations [3, 4, 5, 6, 7] Notes: 3. A12L and A12R are NC pins for CYDC064B16.4. IRR functionality is not supported for the CYDC256B16 device. 5. This pin is A13L for CYDC256B16 device.6. Thi...
CYDC256B16, CYDC128B16,CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev. *E Page 5 of 26 Functional Description The CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 are low-power CMOS 4k, 8k,16k x 16, and 8/16k x 8 dual-port static RAMs. Arbitration schemes are included on the ...
