Cypress CY8CNP102E - Manual

Cypress CY8CNP102E

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Table of Contents:

  • Page 2 – PRELIMINARY; Logic Block Diagram
  • Page 3 – Pinouts
  • Page 5 – PSoC NV Functional Overview
  • Page 6 – Programmable Digital System
  • Page 7 – Development Tools; Figure 2. PSoC Designer Subsystem; PSoC Designer Software Subsystems; Device Editor; P S o C
  • Page 8 – Online Help System; Hardware Tools; Designing with User Modules; User Module and Source Code Development Flows; Figure 3. User Module and Source Code Development Flows; Debugger
  • Page 9 – Cypress nvSRAM user Module; Electrical Specifications; SLIMO
  • Page 10 – Absolute Maximum Ratings
  • Page 11 – DC Electrical Characteristics; DC Chip Level Specifications
  • Page 12 – DC Operational Amplifier Specifications
  • Page 13 – DC Analog Output Buffer Specifications
  • Page 14 – DC Analog Reference Specifications; DC Analog PSoC NV Block Specifications
  • Page 16 – DC Programming Specifications
  • Page 17 – AC Electrical Characteristics; AC Chip Level Specifications
  • Page 18 – AC General Purpose IO Specifications
  • Page 19 – AC Operational Amplifier Specifications
  • Page 20 – AC Analog Output Buffer Specifications
  • Page 21 – AC Programming Specifications
  • Page 22 – V Operation
  • Page 33 – Switching Waveforms; Figure 9. PLL Lock Timing Diagram; P L L; P L L; P L L; P L L
  • Page 34 – Figure 11. External Crystal Oscillator Startup Timing Diagram; S e l e c t
  • Page 35 – Part Numbering Nomenclature; C Y; Ordering Information; Ordering Code; Industrial
  • Page 36 – Packaging Information; Thermal Impedance; Table 41. Thermal Impedance
  • Page 37 – Document History Page; ECN
  • Page 38 – Worldwide Sales and Design Support
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PRELIMINARY

CY8CNP102B, CY8CNP102E

N

onvolatile Programmable System-on-Chip

(

PSoC® NV)

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

,

CA 95134-1709

•

408-943-2600

Document #: 001-43991 Rev. *D

Revised October 20, 2008

Overview

The Cypress nonvolatile Programmable System-on-Chip

(PSoC

®

NV) processor combines a versatile Programmable

System-on-Chip™ (PSoC) core with an infinite endurance

nvSRAM in a single package. The PSoC NV combines an 8-bit

MCU core (M8C), configurable analog and digital functions, a

uniquely flexible IO interface, and a high density nvSRAM. This

creates versatile data logging solutions that provide value

through component integration and programmability. The flexible

core and a powerful development environment work to reduce

design complexity, component count, and development time.

Features

■

Powerful Harvard Architecture Processor

❐

M8C processor speeds
• Up to 12 MHz for 3.3V operation
• Up to 24 MHz for 5V operation

❐

Two 8x8 multiply, 32 bit accumulate

❐

Low power at high speed

■

Operating Voltage

❐

3.3V (CY8CNP102B)

❐

5V (CY8CNP102E)

■

Advanced Peripherals

❐

12 Rail-to-Rail Analog PSoC blocks provide:
• Up to 14 bit ADCs
• Up to 9 bit DACs
• Programmable Gain Amplifiers
• Programmable Filters and Comparators
• 8 Analog channels for simultaneous sampling
• Up to 820 SPS for each channel with 8 channel sampling

and logging

❐

16 Digital PSoC Blocks provide:
• 8 to 32 bit timers, counters, and PWMs
• CRC and PRS Modules
• Up to 4 Full Duplex UARTs
• Multiple SPI

™

Masters and Slaves

❐

Complex Peripherals by Combining Blocks

■

Precision, Programmable Clocking

❐

Internal ±2.5% 24 and 48 MHz Oscillator

❐

24 and 48 MHz with optional 32.768 kHz Crystal

❐

Optional External Oscillator, up to 24 MHz

❐

Internal Oscillator for Watchdog and Sleep

■

Flexible On-Chip Memory

❐

32K Bytes Flash Program Storage

❐

2K Bytes SRAM Data Storage

❐

256K Bytes secure store nvSRAM with data throughput be-

tween 100 KBPS and 1 MBPS

❐

In-System Serial Programming (ISSP)

❐

Partial Flash Updates

❐

Flexible Protection Modes

❐

EEPROM Emulation in Flash

■

Programmable Pin Configurations

❐

33 GPIOs

❐

25 mA Sink on all GPIO

❐

Pull up, Pull down, High Z, Strong, or Open Drain Drive

Modes on all GPIO

❐

Up to 12 Analog Inputs on GPIOs

❐

Analog Outputs with 40 mA on 4 GPIOs

❐

Configurable Interrupt on all GPIOs

■

Additional System Resources

❐

I

2

C Slave, Master, and MultiMaster to 100 Kbps

and 400 Kbps

❐

Watchdog and Sleep Timers

❐

Integrated Supervisory Circuit

❐

On-Chip Precision Voltage Reference

■

Complete Development Tools

❐

Free Development Software (PSoC Designer™)

❐

Full Featured, In Circuit Emulator and Programmer

❐

Full Speed Emulation

❐

C Compilers, Assembler, and Linker

■

Temperature and Packaging

❐

Industrial Temperature Range: -40°C to +85°C

❐

Packaging: 100-pin TQFP

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Summary

Page 2 - PRELIMINARY; Logic Block Diagram

PRELIMINARY CY8CNP102B, CY8CNP102E Document #: 001-43991 Rev. *D Page 2 of 38 Logic Block Diagram [+] Feedback

Page 3 - Pinouts

PRELIMINARY CY8CNP102B, CY8CNP102E Document #: 001-43991 Rev. *D Page 3 of 38 Pinouts Figure 1. Pin Diagram - 100-Pin TQFP Package (14 x 14 x 1.4 mm) Table 1. Pin Definitions - 100-Pin TQFP Pin Number Pin Name Type Pin Definition Digital Analog 1 P0_5 IO IO Analog Column Mux Input and Column Output ...

Page 5 - PSoC NV Functional Overview

PRELIMINARY CY8CNP102B, CY8CNP102E Document #: 001-43991 Rev. *D Page 5 of 38 PSoC NV Functional Overview The PSoC NV provides a versatile microcontroller core (M8C), Flash program memory, nvSRAM data memory, and configurable analog and digital peripheral blocks in a single package. The flexible dig...

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