Cypress CY8C24423A - Manual

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Page 2 – Logic Block Diagram; PSoC Core; Figure 1. Digital System Block Diagram; PSoC Device Characteristics; DIGITAL SYSTEM
Page 3 – Analog System; Figure 2; Figure 2. Analog System Block Diagram
Page 4 – Getting Started; , click the Online Store shopping cart; Table 1. PSoC Device Characteristics; PSoC Part
Page 5 – Development Tools; Figure 3; Figure 3. PSoC Designer Subsystems; PSoC Designer Software Subsystems; Device Editor; PSoC
Page 6 – Hardware Tools; Designing with User Modules; Figure 4. User Module and Source Code Development Flows; Debugger
Page 7 – Document Conventions; Acronyms Used; Table 5; Numeric Naming; Acronym
Page 8 – Pinouts; SSOP
Page 10 – Register Reference; Register Conventions; Abbreviations Used; Register Mapping Tables; Note; In the following register mapping tables, blank fields are; Table 5. Abbreviations; Access is bit specific
Page 11 – Table 6. Register Map Bank 0 Table: User Space
Page 12 – Table 7. Register Map Bank 1 Table: Configuration Space
Page 14 – Electrical Specifications; Valid
Page 15 – Thermal Impedances per Package
Page 16 – DC Electrical Characteristics; DC Chip-Level Specifications; DC General Purpose IO Specifications; C. Typical parameters apply to 5V at 25
Page 17 – DC Operational Amplifier Specifications
Page 19 – DC Analog Reference Specifications
Page 21 – AC Electrical Characteristics; AC Chip-Level Specifications
Page 24 – LPC response time
Page 25 – AC Digital Block Specifications
Page 28 – Packaging Information; Important Note; the emulation tools’ dimensions, refer to the document titled
Page 30 – Ordering Information; Ordering Code Definitions
Page 31 – Document History Page; Worldwide Sales and Design Support; ECN

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CY8C24223A, CY8C24423A

PSoC

Programmable System-on-Chip™

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Document Number: 3-12029 Rev. *E

Revised December 11, 2008

Features

■

Powerful Harvard Architecture Processor

❐

M8C Processor Speeds to 12 MHz

❐

8x8 Multiply, 32-Bit Accumulate

❐

Low Power at High Speed

❐

4.75V to 5.25V Operating Voltage

❐

Extended Temperature Range: -40°C to +125°C

■

Advanced Peripherals (PSoC Blocks)

❐

Six Rail-to-Rail Analog PSoC Blocks Provide:
• Up to 14-Bit ADCs
• Up to 9-Bit DACs
• Programmable Gain Amplifiers
• Programmable Filters and Comparators

❐

Four Digital PSoC Blocks Provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
• Full-Duplex UART
• Multiple SPI

™

Masters or Slaves

• Connectable to all GPIO Pins

❐

Complex Peripherals by Combining Blocks

■

Precision, Programmable Clocking

❐

Internal ± 4% 24 MHz Oscillator

❐

High Accuracy 24 MHz with Optional 32 kHz Crystal and PLL

❐

Optional External Oscillator, up to 24 MHz

❐

Internal Oscillator for Watchdog and Sleep

■

Flexible On-Chip Memory

❐

4K Bytes Flash Program Storage 100 Erase/Write Cycles

❐

256 Bytes SRAM Data Storage

❐

In-System Serial Programming (ISSP)

❐

Partial Flash Updates

❐

Flexible Protection Modes

■

Programmable Pin Configurations

❐

25 mA Sink on All GPIO

❐

Pull Up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on All GPIO

❐

Up to Ten Analog Inputs on GPIO

❐

Two 30 mA Analog Outputs on GPIO

❐

Configurable Interrupt on All GPIO

■

Additional System Resources

❐

™

Slave, Master, and Multi-Master to 400 kHz

❐

Watchdog and Sleep Timers

❐

User-Configurable Low Voltage Detection

❐

Integrated Supervisory Circuit

❐

On-Chip Precision Voltage Reference

■

Complete Development Tools

❐

Free Development Software (PSoC Designer™)

❐

Full-Featured, In-Circuit Emulator and Programmer

❐

Full Speed Emulation

❐

Complex Breakpoint Structure

❐

128K Bytes Trace Memory

DIGITAL SYSTEM

SRAM

256 Bytes

Interrupt

Controller

Sleep and
Watchdog

Multiple Clock Sources

(Includes IMO, ILO, PLL, and ECO)

Global Digital Interconnect

Global Analog Interconnect

PSoC CORE

CPU Core (M 8C)

SROM

Flas h 4K

Digital

Block Array

Multiply
Accum .

Internal
Voltage

Ref.

Digital

Clocks

POR and LVD

Sys tem Res ets

Decim ator

SYSTEM RESOURCES

ANALOG SYSTEM

Analog

Ref

Analog

Input

Muxing

(1 Row,

4 Blocks )

Port 2

Port 1

Port 0

A nalog

Driv ers

System Bus

Analog

Block

Array

(2 Colum ns ,

6 Blocks )

Logic Block Diagram

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Summary

Page 2 - Logic Block Diagram; PSoC Core; Figure 1. Digital System Block Diagram; PSoC Device Characteristics; DIGITAL SYSTEM

CY8C24223A, CY8C24423A Document Number: 3-12029 Rev. *E Page 2 of 31 PSoC ® Functional Overview The PSoC ® family consists of many Mixed-Signal Array with On-Chip Controller devices. These devices are designed toreplace multiple traditional MCU-based system components withone, low cost single-chip p...

Page 3 - Analog System; Figure 2; Figure 2. Analog System Block Diagram

CY8C24223A, CY8C24423A Document Number: 3-12029 Rev. *E Page 3 of 31 Analog System The Analog System is composed of six configurable blocks, eachcomprised of an opamp circuit allowing the creation of complexanalog signal flows. Analog peripherals are very flexible and canbe customized to support spe...

Page 4 - Getting Started; , click the Online Store shopping cart; Table 1. PSoC Device Characteristics; PSoC Part

CY8C24223A, CY8C24423A Document Number: 3-12029 Rev. *E Page 4 of 31 Additional System Resources System Resources, some of which have been previously listed,provide additional capability useful to complete systems.Additional resources include a multiplier, decimator, switch modepump, low voltage det...