Cypress CY8C24423 - Manual

Cypress CY8C24423

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Table of Contents:

  • Page 2 – Logic Block Diagram; PSoC Core; Figure 1. Digital System Block Diagram; PSoC Device Characteristics; Digital PSoC Block Array
  • Page 3 – Analog System; Figure 2. Analog System Block Diagram; Block Array; Analog Reference
  • Page 4 – Getting Started; , click the Online Store shopping cart; Table 1. PSoC Device Characteristics
  • Page 5 – Development Tools; The Cypress MicroSystems PSoC Designer is a Microsoft; Figure 3. PSoC Designer Subsystems; PSoC Designer Software Subsystems; Device Editor; Designer
  • Page 6 – Hardware Tools; Figure 4. PSoC Development Tool Kit
  • Page 7 – Figure 5. User Module and Source Code Development Flows; Document Conventions; Table 7; Acronym
  • Page 8 – Pinouts; PDIP
  • Page 10 – MLF
  • Page 11 – Register Reference; PSoC Programmable; Register Conventions; Abbreviations Used; Register Mapping Tables; Note; In the following register mapping tables, blank fields are; Table 7. Abbreviations; RW
  • Page 12 – Table 8. Register Map Bank 0 Table: User Space
  • Page 13 – Table 9. Register Map Bank 1 Table: Configuration Space
  • Page 15 – Electrical Specifications; CPU Frequency
  • Page 16 – Thermal Impedances per Package
  • Page 17 – DC Electrical Characteristics; DC Chip-Level Specifications
  • Page 19 – dB; PSRR; Supply Voltage Rejection Ratio
  • Page 21 – DC Analog Output Buffer Specifications
  • Page 22 – DC Switch Mode Pump Specifications
  • Page 23 – DC Analog Reference Specifications
  • Page 26 – DC Programming Specifications
  • Page 27 – AC Electrical Characteristics; AC Chip-Level Specifications
  • Page 28 – PLL; PLL; PLL; PLL
  • Page 29 – AC General Purpose IO Specifications; GPIO
  • Page 30 – AC Operational Amplifier Specifications
  • Page 32 – AC Digital Block Specifications
  • Page 33 – AC Analog Output Buffer Specifications
  • Page 35 – SDA
  • Page 36 – Packaging Information
  • Page 42 – Ordering Information; Ordering Code Definitions
  • Page 43 – Document History Page; Worldwide Sales and Design Support
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CY8C24123

CY8C24223, CY8C24423

PSoC

®

Programmable System-on-Chip™

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

,

CA 95134-1709

•

408-943-2600

Document Number: 38-12011 Rev. *G

Revised December 11, 2008

Features

■

Powerful Harvard Architecture Processor

❐

M8C Processor Speeds to 24 MHz

❐

8x8 Multiply, 32-Bit Accumulate

❐

Low Power at High Speed

❐

3.0 to 5.25 V Operating Voltage

❐

Operating Voltages Down to 1.0V Using On-Chip Switch
Mode Pump (SMP)

❐

Industrial Temperature Range: -40°C to +85°C

■

Advanced Peripherals (PSoC Blocks)

❐

Six Rail-to-Rail Analog PSoC Blocks Provide:
• Up to 14-Bit ADCs
• Up to 8-Bit DACs
• Programmable Gain Amplifiers
• Programmable Filters and Comparators

❐

Four Digital PSoC Blocks Provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
• Full-Duplex UART
• Multiple SPI

™

Masters or Slaves

• Connectable to all GPIO Pins

❐

Complex Peripherals by Combining Blocks

■

Precision, Programmable Clocking

❐

Internal ± 2.5% 24/48 MHz Oscillator

❐

High-Accuracy 24 MHz with Optional 32 kHz Crystal and PLL

❐

Optional External Oscillator, up to 24 MHz

❐

Internal Oscillator for Watchdog and Sleep

■

Flexible On-Chip Memory

❐

4K Bytes Flash Program Storage 50,000 Erase/Write Cycles

❐

256 Bytes SRAM Data Storage

❐

In-System Serial Programming (ISSP

™

)

❐

Partial Flash Updates

❐

Flexible Protection Modes

❐

EEPROM Emulation in Flash

■

Programmable Pin Configurations

❐

25 mA Sink on all GPIO

❐

Pull up, Pull down, High Z, Strong, or Open Drain Drive
Modes on all GPIO

❐

Up to 10 Analog Inputs on GPIO

❐

Two 30 mA Analog Outputs on GPIO

❐

Configurable Interrupt on all GPIO

■

Additional System Resources

❐

I

2

C

™

Slave, Master, and Multi-Master to 400 kHz

❐

Watchdog and Sleep Timers

❐

User-Configurable Low Voltage Detection

❐

Integrated Supervisory Circuit

❐

On-Chip Precision Voltage Reference

■

Complete Development Tools

❐

Free Development Software (PSoC Designer™)

❐

Full-Featured, In-Circuit Emulator and Programmer

❐

Full Speed Emulation

❐

Complex Breakpoint Structure

❐

128K Bytes Trace Memory

DIGITAL SYSTEM

SRAM

256 Bytes

Interrupt

Controller

Sleep and
Watchdog

Multiple Clock Sources

(Includes IMO, ILO, PLL, and ECO)

Global Digital Interconnect

Global Analog Interconnect

PSoC CORE

CPU Core (M8C)

SROM

Flash 4K

Digital

Block Array

Multiply
Accum.

Switch

Mode

Pump

Internal
Voltage

Ref.

Digital

Clocks

POR and LVD

System Resets

Decimator

SYSTEM RESOURCES

ANALOG SYSTEM

Analog

Ref

Analog

Input

Muxing

I

2

C

(1 Rows,

4 Blocks)

Port 2

Port 1

Port 0

Analog
Drivers

System Bus

Analog

Block

Array

(2 Columns,

6 Blocks)

Logic Block Diagram

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Summary

Page 2 - Logic Block Diagram; PSoC Core; Figure 1. Digital System Block Diagram; PSoC Device Characteristics; Digital PSoC Block Array

CY8C24123 CY8C24223, CY8C24423 Document Number: 38-12011 Rev. *G Page 2 of 43 PSoC ® Functional Overview The PSoC ® family consists of many Mixed Signal Array with On-Chip Controller devices. These devices are designed toreplace multiple traditional MCU-based system components withone, low cost sing...

Page 3 - Analog System; Figure 2. Analog System Block Diagram; Block Array; Analog Reference

CY8C24123 CY8C24223, CY8C24423 Document Number: 38-12011 Rev. *G Page 3 of 43 Analog System The Analog System is composed of six configurable blocks, eachcomprised of an opamp circuit allowing the creation of complexanalog signal flows. Analog peripherals are very flexible and canbe customized to su...

Page 4 - Getting Started; , click the Online Store shopping cart; Table 1. PSoC Device Characteristics

CY8C24123 CY8C24223, CY8C24423 Document Number: 38-12011 Rev. *G Page 4 of 43 Additional System Resources System Resources, some of which have been previously listed,provide additional capability useful to complete systems.Additional resources include a multiplier, decimator, switch modepump, low vo...

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