Cypress CY8C23533 - Manual

Cypress CY8C23533

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Table of Contents:

  • Page 2 – PSoC Functional Overview; Logic Block Diagram; PSoC Core; Digital System; Figure 1. Digital System Block Diagram; PSoC Device Character-; Digital PSoC Block Array
  • Page 3 – Analog System; Figure 2. Analog System Block Diagram
  • Page 4 – Getting Started; at; Table 1. PSoC Device Characteristics; Yes
  • Page 5 – Development Tools; PSoC Designer; Figure 3. PSoC Designer Subsystems; PSoC Designer Software Subsystems; Device Editor; C Language Compiler.; Co; PSoC
  • Page 6 – Hardware Tools; Designing with User Modules; Figure 4. User Module/Source Code Development Flows; Debugger
  • Page 7 – Document Conventions; Acronyms Used; Electrical; Numeric Naming
  • Page 8 – Pinouts; QFN
  • Page 9 – SSOP
  • Page 10 – Register Reference; Register Conventions; Abbreviations Used; Register Mapping Tables
  • Page 11 – Table 6. Register Map Bank 0 Table: User Space
  • Page 12 – Table 7. Register Map Bank 1 Table: Configuration Space
  • Page 14 – Electrical Specifications; Specifications are valid for -40°C; Table 8. Units of Measure; Symbol; CPU Fre que ncy; IM; SLIMO; Figure 7. Voltage versus CPU Frequency
  • Page 15 – ances by Package
  • Page 16 – DC Electrical Characteristics; DC Chip-Level Specifications
  • Page 17 – DC General Purpose IO Specifications
  • Page 18 – DC Operational Amplifier Specifications
  • Page 19 – DC Low Power Comparator Specifications
  • Page 20 – DC Analog Output Buffer Specifications
  • Page 21 – DC Analog Reference Specifications
  • Page 23 – DC Programming Specifications
  • Page 24 – SAR8 ADC DC Specifications
  • Page 25 – AC Electrical Characteristics; AC Chip-Level Specifications; Figure 8
  • Page 28 – Rising Settling Time from 80% of; Falling Settling Time from 20% of; BW
  • Page 29 – Figure 16. Typical Opamp Noise
  • Page 31 – AC Analog Output Buffer Specifications
  • Page 33 – SDA
  • Page 34 – Packaging Information; BOTTOM VIEW; SEE NOTE 1
  • Page 36 – Ordering Information
  • Page 37 – Document History Page; Worldwide Sales and Design Support
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CY8C23433, CY8C23533

PSoC

®

Programmable System-on-Chip™

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

,

CA 95134-1709

•

408-943-2600

Document Number: 001-44369 Rev. *B

Revised December 05, 2008

Features

■

Powerful Harvard Architecture Processor

❐

M8C Processor Speeds to 24 MHz

❐

8x8 Multiply, 32-Bit Accumulate

❐

Low Power at High Speed

❐

3.0 to 5.25V Operating Voltage

❐

Industrial Temperature Range: -40°C to +85°C

■

Advanced Peripherals (PSoC Blocks)

❐

4 Rail-to-Rail analog PSoC Blocks Provide:
• Up to 14-Bit ADCs
• Up to 8-Bit DACs
• Programmable Gain Amplifiers
• Programmable Filters and Comparators

❐

4 Digital PSoC Blocks Provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
• Full-Duplex UART
• Multiple SPI

™

Masters or Slaves

• Connectable to All GPIO Pins

❐

Complex Peripherals by Combining Blocks

❐

High-Speed 8-Bit SAR ADC Optimized for Motor Control

■

Precision, Programmable Clocking

❐

Internal ±2.5% 24/48 MHz Oscillator

❐

High Accuracy 24 MHz with Optional 32 kHz Crystal and PLL

❐

Optional External Oscillator, up to 24 MHz

❐

Internal Oscillator for Watchdog and Sleep

■

Flexible On-Chip Memory

❐

8K Bytes Flash Program Storage 50,000 Erase/Write Cycles

❐

256 Bytes SRAM Data Storage

❐

In-System Serial Programming (ISSP)

❐

Partial Flash Updates

❐

Flexible Protection Modes

❐

EEPROM Emulation in Flash

■

Programmable Pin Configurations

❐

25 mA Sink on all GPIO

❐

Pull up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on All GPIO

❐

Up to Ten Analog Inputs on GPIO

❐

Two 30 mA Analog Outputs on GPIO

❐

Configurable Interrupt on All GPIO

■

Additional System Resources

❐

I

2

C

™

Slave, Master, and Multi-Master to 400 kHz

❐

Watchdog and Sleep Timers

❐

User-Configurable Low Voltage Detection

❐

Integrated Supervisory Circuit

❐

On-chip Precision Voltage Reference

■

Complete Development Tools

❐

Free Development Software (PSoC Designer™)

❐

Full-Featured In-Circuit Emulator and Programmer

❐

Full Speed Emulation

❐

Complex Breakpoint Structure

❐

128K Bytes Trace Memory

DIGITAL SYSTEM

SRAM

256 Bytes

Interrupt

Controller

Sleep and
Watchdog

Multiple Clock Sources

(Includes IMO, ILO, PLL, and ECO)

Global Digital Interconnect

Global Analog Interconnect

PSoC CORE

CPU Core (M 8C)

SROM

Flas h 8K

Digital

Block
Array

Multiply
Accum .

Internal
Voltage

Ref.

Digital

Clocks

POR and LVD

Sys tem Res ets

Decim ator

SYSTEM RESOURCES

ANALOG SYSTEM

Analog

Ref

Analog

Input

Muxing

I

2

C

Port 2

Port 1

Port 0

A nalog
Driv ers

System Bus

Analog

Block Array

1 Row

4 Blocks

2 Colum ns

4 Blocks

SAR8 ADC

Port 3

Logic Block Diagram

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Summary

Page 2 - PSoC Functional Overview; Logic Block Diagram; PSoC Core; Digital System; Figure 1. Digital System Block Diagram; PSoC Device Character-; Digital PSoC Block Array

CY8C23433, CY8C23533 Document Number: 001-44369 Rev. *B Page 2 of 37 PSoC Functional Overview The PSoC family consists of many mixed-signal array withOn-Chip Controller devices. These devices are designed toreplace multiple traditional MCU-based system components witha low cost single-chip programma...

Page 3 - Analog System; Figure 2. Analog System Block Diagram

CY8C23433, CY8C23533 Document Number: 001-44369 Rev. *B Page 3 of 37 Analog System The Analog system consists of an 8-bit SAR ADC and fourconfigurable blocks. The programmable 8-bit SAR ADC is anoptimized ADC that runs up to 300 Ksps, with monotonicguarantee. It also has the features to support a mo...

Page 4 - Getting Started; at; Table 1. PSoC Device Characteristics; Yes

CY8C23433, CY8C23533 Document Number: 001-44369 Rev. *B Page 4 of 37 Additional System Resources System Resources, some of which are listed in the previoussections, provide additional capability useful to completesystems. Additional resources include a multiplier, decimator,low voltage detection, an...

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