Cypress CY8C22113 - Manual
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Table of Contents:
- Page 2 – PSoCTM Overview; The Digital System; Digital System Block Diagram; teristics” on page 3; The Analog System; DIGITAL SYSTEM
- Page 3 – “PSoC Device Characteris-; Analog System Block Diagram; Additional System Resources; PSoC Device Characteristics
- Page 4 – Getting Started; Development Kits; Development Tools; The Cypress MicroSystems PSoC Designer is a Microsoft; PSoC Designer Subsystems; Designer
- Page 5 – PSoC Designer Software Subsystems; Device Editor; Hardware Tools; PSoC Development Tool Kit
- Page 6 – Debugger
- Page 7 – Document Conventions; Acronyms Used; lists all the abbreviations; Numeric Naming; Table of Contents
- Page 8 – Pin Information; Pinouts; PDIP
- Page 9 – MLF
- Page 10 – Register Reference; Register Conventions; Abbreviations Used; Register Mapping Tables
- Page 11 – Register Reference; Register Map Bank 0 Table: User Space
- Page 12 – Register Map Bank 1 Table: Configuration Space
- Page 13 – Electrical Specifications; Specifications are valid for -40; Figure 3-1. Voltage versus Operating Frequency
- Page 14 – Electrical Specifications; Absolute Maximum Ratings
- Page 15 – DC Electrical Characteristics; DC Chip-Level Specifications
- Page 16 – DC Operational Amplifier Specifications; C, respectively. Typical parameters apply to 5V and 3.3V at 25; Table 3-6. 5V DC Operational Amplifier Specifications
- Page 18 – DC Analog Output Buffer Specifications; Table 3-8. 5V DC Analog Output Buffer Specifications
- Page 19 – DC Analog Reference Specifications; Table 3-10. 5V DC Analog Reference Specifications; Table 3-12. DC Analog PSoC Block Specifications
- Page 20 – DC POR and LVD Specifications; Table 3-13. DC POR and LVD Specifications
- Page 21 – DC Programming Specifications; Table 3-14. DC Programming Specifications
- Page 22 – AC Electrical Characteristics; AC Chip-Level Specifications
- Page 24 – AC General Purpose IO Specifications
- Page 25 – AC Operational Amplifier Specifications; Table 3-17. 5V AC Operational Amplifier Specifications
- Page 27 – AC Digital Block Specifications; Table 3-19. AC Digital Block Specifications
- Page 28 – AC Analog Output Buffer Specifications; Table 3-20. 5V AC Analog Output Buffer Specifications
- Page 29 – AC External Clock Specifications; Table 3-22. 5V AC External Clock Specifications; Table 3-24. AC Programming Specifications
- Page 30 – AC I; Figure 3-8. Definition for Timing for Fast/Standard Mode on the I; SDA
- Page 31 – Packaging Information; Packaging Dimensions
- Page 32 – Packaging Information
- Page 34 – Thermal Impedances; Table 4-1. Thermal Impedances per Package; Table 4-2: Typical Package Capacitance on Crystal Pins
- Page 35 – Ordering Information; Ordering Code Definitions
- Page 36 – Sales and Company Information; “Getting Started” on page 4; Cypress MicroSystems; Revision History; Company Information –; Table 6-1. CY8C22x13 Data Sheet Revision History
June 2004
© Cypress MicroSystems, Inc. 2004 — Document No. 38-12009 Rev. *E
1
PSoC™ Mixed Signal Array
Final Data Sheet
CY8C22113 and CY8C22213
PSoC™ Functional Overview
The PSoC™ family consists of many Mixed Signal Array with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU-based system components
with one, low cost single-chip programmable device. PSoC
devices include configurable blocks of analog and digital logic,
as well as programmable interconnects. This architecture
allows the user to create customized peripheral configurations
that match the requirements of each individual application.
Additionally, a fast CPU, Flash program memory, SRAM data
memory, and configurable IO are included in a range of conve-
nient pinouts and packages.
The PSoC architecture, as illustrated on the left, is comprised of
four main areas: PSoC Core, Digital System, Analog System,
and System Resources. Configurable global busing allows all
the device resources to be combined into a complete custom
system. The PSoC CY8C22x13 family can have up to two IO
ports that connect to the global digital and analog interconnects,
providing access to 4 digital blocks and 3 analog blocks.
The PSoC Core
The PSoC Core is a powerful engine that supports a rich fea-
ture set. The core includes a CPU, memory, clocks, and config-
urable GPIO (General Purpose IO).
The M8C CPU core is a powerful processor with speeds up to
24 MHz, providing a four MIPS 8-bit Harvard architecture micro-
Features
■
Powerful Harvard Architecture Processor
❐
M8C Processor Speeds to 24 MHz
❐
Low Power at High Speed
❐
3.0 to 5.25 V Operating Voltage
❐
Industrial Temperature Range: -40°C to +85°C
■
Advanced Peripherals (PSoC Blocks)
❐
3 Rail-to-Rail Analog PSoC Blocks Provide:
- Up to 14-Bit ADCs
- Up to 9-Bit DACs
- Programmable Gain Amplifiers
- Programmable Filters and Comparators
❐
4 Digital PSoC Blocks Provide:
- 8- to 32-Bit Timers, Counters, and PWMs
- CRC and PRS Modules
- Full-Duplex UART
- SPI
Masters or Slaves
- Connectable to all GPIO Pins
❐
Complex Peripherals by Combining Blocks
■
Precision, Programmable Clocking
❐
Internal ±2.5% 24/48 MHz Oscillator
❐
High-Accuracy 24 MHz with Optional 32.768
kHz Crystal and PLL
❐
Optional External Oscillator, up to 24 MHz
❐
Internal Oscillator for Watchdog and Sleep
■
Flexible On-Chip Memory
❐
2K Bytes Flash Program Storage 50,000
Erase/Write Cycles
❐
256 Bytes SRAM Data Storage
❐
In-System Serial Programming (ISSP
)
❐
Partial Flash Updates
❐
Flexible Protection Modes
❐
EEPROM Emulation in Flash
■
Programmable Pin Configurations
❐
25 mA Sink on all GPIO
❐
Pull up, Pull down, High Z, Strong, or Open
Drain Drive Modes on all GPIO
❐
Up to 8 Analog Inputs on GPIO
❐
One 30 mA Analog Outputs on GPIO
❐
Configurable Interrupt on all GPIO
■
Additional System Resources
❐
I
2
C
Slave, Master, and Multi-Master to
400 kHz
❐
Watchdog and Sleep Timers
❐
User-Configurable Low Voltage Detection
❐
Integrated Supervisory Circuit
❐
On-Chip Precision Voltage Reference
■
Complete Development Tools
❐
Free Development Software
(PSoC™ Designer)
❐
Full-Featured, In-Circuit Emulator and
Programmer
❐
Full Speed Emulation
❐
Complex Breakpoint Structure
❐
128K Bytes Trace Memory
DIGITAL SYSTEM
SRAM
256 Bytes
SYSTEM BUS
Interrupt
Controller
Sleep and
Watchdog
Global Digital Interconnect
Global Analog Interconnect
PSoC CORE
CPU Core (M8C)
SROM
Flash 2K
Digital
Block Array
(1 Row,
4 Blocks)
I
2
C
Internal
Voltage
Ref.
Digital
Clocks
POR and LVD
System Resets
Decimator
SYSTEM RESOURCES
ANALOG SYSTEM
Analog
Ref
Analog
Input
Muxing
Port 1
Port 0
Analog
Drivers
Analog
Block
Array
(1 Column,
3 Blocks)
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
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Summary
June 3, 2004 Document No. 38-12009 Rev. *E 2 CY8C22x13 Final Data Sheet PSoC™ Overview processor. The CPU utilizes an interrupt controller with 10 vec-tors, to simplify programming of real time embedded events.Program execution is timed and protected using the includedSleep and Watch Dog Timers (WDT...
June 3, 2004 Document No. 38-12009 Rev. *E 3 CY8C22x13 Final Data Sheet PSoC™ Overview Analog blocks are provided in columns of three, which includesone CT (Continuous Time) and two SC (Switched Capacitor)blocks. The number of blocks is dependant on the device familywhich is detailed in the table ti...
June 3, 2004 Document No. 38-12009 Rev. *E 4 CY8C22x13 Final Data Sheet PSoC™ Overview Getting Started The quickest path to understanding the PSoC silicon is by read-ing this data sheet and using the PSoC Designer IntegratedDevelopment Environment (IDE). This data sheet is an over-view of the PSoC i...
