Cypress CY7C68321C - Manual

Cypress CY7C68321C

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Table of Contents:

  • Page 2 – Applications; Additional Resources; Introduction; Figure 1; Figure 1. Simplified Pinout Selection Flowchart
  • Page 8 – CY4615C reference design kit CD; CC; CC; CC; CC; RESERVED
  • Page 9 – “VBUSPWRD” on
  • Page 10 – “DRVPWRVLD” on; “GPIO Pins” on
  • Page 11 – Figure 7
  • Page 12 – Table 3. Interrupt Data Bitmap
  • Page 13 – Figure 8. SYSIRQ Latching Algorithm; DRVPWRVLD
  • Page 14 – Reset and Power Considerations,; Pin
  • Page 15 – HID Functions for Button Controls; Table 5; Functional Overview; USB Signaling Speed; ATA Interface; USB; Table 5. HID Data Bitmap
  • Page 18 – Operating Modes; Operational Mode Selection Flow; “Fused Memory Data” on page 19; Figure 10. Operational Mode Selection Flow
  • Page 20 – MfgCB
  • Page 21 – EEPROM Organization; EEPROM are arranged as follows. In; Figure 11. Snapshot of ‘AT2LP Blaster’ Utility
  • Page 35 – Parameter
  • Page 36 – AC Electrical Characteristics; ATA Timing Characteristics; Ordering Information; Part Number; 6 SSOP Lead-free for battery-powered designs
  • Page 37 – Package Diagrams
  • Page 38 – Figure 13. 56-lead Shrunk Small Outline Package 056
  • Page 39 – General PCB Layout Recommendations For USB Mass Storage Designs; • EZ-USB FX2LP PCB Design Recommendations
  • Page 40 – Quad Flat Package No Leads (QFN) Package Design Notes; Surface Mount Assembly of AMKOR’s; Figure 15. Cross-Section of the Area Under the QFN Package; is a plot of solder mask pattern and; Other Design Considerations; Proper Power Up Sequence; PCB Material
  • Page 41 – Purchase of I
  • Page 42 – Document History Paged; Issue Date; See ECN
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EZ-USB AT2LP™ USB 2.0 to ATA/ATAPI Bridge

CY7C68300C/CY7C68301C
CY7C68320C/CY7C68321C

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

,

CA 95134-1709

•

408-943-2600

Document 001-05809 Rev. *A

Revised November 30, 2006

Features

• Fixed-function mass storage device—requires no firmware

• Two power modes: Self-powered and USB bus-powered to

enable bus powered CF readers and truly portable USB
hard drives

• Certified compliant for USB 2.0 (TID# 40490119), the USB

Mass Storage Class, and the USB Mass Storage Class
Bulk-Only Transport (BOT) Specification

• Operates at high-speed (480 Mbps) or full-speed (12 Mbps)

USB

• Complies with ATA/ATAPI-6 specification

• Supports 48 bit addressing for large hard drives

• Supports ATA security features

• Supports any ATA command with the ATACB function

• Supports mode page 5 for BIOS boot support

• Supports ATAPI serial number VPD page retrieval for Digital

Rights Management (DRM) compatibility

• Supports PIO modes 0, 3, and 4, multiword DMA mode 2,

and UDMA modes 2, 3, and 4

• Uses one small external serial EEPROM for storage of USB

descriptors and device configuration data

• ATA interface IRQ signal support

• Supports one or two ATA/ATAPI devices

• Supports CompactFlash and one ATA/ATAPI device

• Supports board-level manufacturing test using the USB I/F

• Can place the ATA interface in high impedance (Hi-Z) to

allow sharing of the ATA bus with another controller (i.e., an
IEEE-1394 to ATA bridge chip or MP3 Decoder)

• Low-power 3.3V operation

• Fully compatible with native USB mass storage class drivers

• Cypress mass storage class drivers available for Windows

(98SE, ME, 2000, XP) and Mac OS X operating systems

Features (CY7C68320C/CY7C68321C only)

• Supports HID interface or custom GPIOs to enable features

such as single button backup, power-off, LED-based notifi-
cation, etc.

• 56-pin QFN and 100-pin TQFP lead-free packages

• CY7C68321C is ideal for battery-powered designs

• CY7C68320C is ideal for self- and bus-powered designs

Features (CY7C68300C/CY7C68301C only)

• Pin-compatible with CY7C68300A (using Backward

Compatibility mode)

• 56-pin SSOP and 56-pin QFN lead-free packages

• CY7C68301C is ideal for battery-powered designs

• CY7C68300C is ideal for self- and bus-powered designs

USB 2.0

Tranceiver

CY Smart USB

FS/HS Engine

4 kByte FIFO

PLL

I

2

C Bus Master

ATA

Interface

Logic

Data

Control

24

MHz

XTAL

16 Bit ATA Data

USB

D+

D-

Internal Control Logic

VBUS

ATA Interface

Control Signals

Misc control signals and GPIO

SDA

SCL

ATA 3-state Control

Re

s

e

t

Block Diagram

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Summary

Page 2 - Applications; Additional Resources; Introduction; Figure 1; Figure 1. Simplified Pinout Selection Flowchart

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321C Document 001-05809 Rev. *A Page 2 of 42 Applications The CY7C68300C/301C and CY7C68320C/321A implementa USB 2.0 bridge for all ATA/ATAPI-6 compliant mass storagedevices, such as the following: • Hard drives • CD-ROM, CD-R/W • DVD-ROM, DVD-RAM, DVD±R/W • MP3...

Page 8 - CY4615C reference design kit CD; CC; CC; CC; CC; RESERVED

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321C Document 001-05809 Rev. *A Page 8 of 42 Pin Descriptions The following table lists the pinouts for the 56-pin SSOP, 56-pinQFN and 100-pin TQFP package options for the AT2LP. Referto the “Pin Diagrams” on page 3 for differences between the 68300C/01C and 683...

Page 9 - “VBUSPWRD” on

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321C Document 001-05809 Rev. *A Page 9 of 42 30 16 23 SDA IO Data signal for I 2 C interface. (See “SCL, SDA” on page 11 ). Apply a 2.2k pull up resistor. 3132 N/A N/A NC No connect. 33 17 24 V CC PWR V CC . Connect to 3.3V power source. 34 18 25 DD0 IO [1] Hi-Z...

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