Cypress CY7C68034 - Manual
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Table of Contents:
- Page 2 – Default NAND Firmware Features; Mass Storage; Overview
- Page 3 – Functional Overview; USB Signaling Speed; Special Function Registers; C Bus; DVB Unit; GPS Unit; 2-pF capacitor values assumes a trace capacitance
- Page 6 – Table 4
- Page 8 – Figure 6. Internal Code Memory; RESET
- Page 9 – Endpoint RAM; — Bidirectional endpoint zero, 64-byte buffer; Figure 8. Endpoint Configuration; Table 6. Default Full-Speed Alternate Settings
- Page 10 – Default High-Speed Alternate Settings; External FIFO Interface; Architecture; GPIF; Table 7. Default High-Speed Alternate Settings
- Page 11 – ECC Generation; C Port Pins
- Page 12 – Pin Assignments; Figure 9; Figure 9. Port and Signal Mapping
- Page 18 – Register Summary
- Page 24 – Absolute Maximum Ratings; Operating Conditions
- Page 28 – Sequence Diagram of a Single and Burst Asynchronous Read; ns; ns
- Page 29 – Sequence Diagram of a Single and Burst Asynchronous Write
- Page 31 – PCB Layout Recommendations; Surface Mount Assembly of AMKOR’s; Figure 21. Cross-section of the Area Underneath the QFN Package.; PCB Material
- Page 33 – Document History Page; Issue Date
EZ-USB NX2LP-Flex™ Flexible USB NAND Flash Controller
CY7C68033/CY7C68034
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 001-04247 Rev. *D
Revised September 21, 2006
CY7C68033/CY7C68034 Silicon Features
• Certified compliant for Bus- or Self-powered USB 2.0
operation (TID# 40490118)
• Single-chip, integrated USB 2.0 transceiver and smart SIE
• Ultra low power – 43 mA typical current draw in any mode
• Enhanced 8051 core
— Firmware runs from internal RAM, which is downloaded
from NAND flash at startup
— No external EEPROM required
• 15 KBytes of on-chip Code/Data RAM
— Default NAND firmware ~8 kB
— Default free space ~7 kB
• Four programmable BULK/INTERRUPT/ISOCHRONOUS
endpoints
— Buffering options: double, triple, and quad
• Additional programmable (BULK/INTERRUPT) 64-byte
endpoint
• SmartMedia Standard Hardware ECC generation with 1-bit
correction and 2-bit detection
• GPIF (General Programmable Interface)
— Allows direct connection to most parallel interfaces
— Programmable waveform descriptors and configuration
registers to define waveforms
— Supports multiple Ready (RDY) inputs and Control (CTL)
outputs
• 12 fully-programmable GPIO pins
• Integrated, industry-standard enhanced 8051
— 48-MHz, 24-MHz, or 12-MHz CPU operation
— Four clocks per instruction cycle
— Three counter/timers
— Expanded interrupt system
— Two data pointers
• 3.3V operation with 5V tolerant inputs
• Vectored USB interrupts and GPIF/FIFO interrupts
• Separate data buffers for the Set-up and Data portions of a
CONTROL transfer
• Integrated I
2
C™ controller, runs at 100 or 400 kHz
• Four integrated FIFOs
— Integrated glue logic and FIFOs lower system cost
— Automatic conversion to and from 16-bit buses
— Master or slave operation
— Uses external clock or asynchronous strobes
— Easy interface to ASIC and DSP ICs
• Available in space saving, 56-pin QFN package
CY7C68034 Only Silicon Features:
• Ideal for battery powered applications
— Suspend current: 100
μ
A (typ.)
CY7C68033 Only Silicon Features:
• Ideal for non-battery powered applications
— Suspend current: 300
μ
A (typ.)
x20
PLL
/0.5
/1.0
/2.0
8051 Core
12/24/48 MHz,
four clocks/cycle
V
CC
1.5k
D+
D–
A
d
d
res
s
(1
6)/D
at
a
Bus
(8
)
GPIF
CY
Smart
USB
1.1/2.0
Engine
USB
2.0
XCVR
Additional I/Os
CTL (3)
RDY (2)
8/16
ECC
NAND
Boot Logic
(ROM)
NX2LP-Flex
24 MHz
Ext. Xtal
Connected for
full-speed USB
Integrated full- and
high-speed XCVR
15 kB
RAM
General Programmable
I/F to ASIC/DSP or bus
standards such as 8-bit
NAND, EPP, etc.
4 kB
FIFO
Up to 96 MB/s burst rate
High-performance,
enhanced 8051 core
with low power options
‘Soft Configuration’ enables
easy firmware changes
FIFO and USB endpoint memory
(master or slave modes)
Enhanced USB core
simplifies 8051 code
I
2
C
Master
Block Diagram
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Summary
CY7C68033/CY7C68034 Document #: 001-04247 Rev. *D Page 2 of 33 Default NAND Firmware Features Because the NX2LP-Flex™ is intended for NANDFlash-based USB mass storage applications, a defaultfirmware image is included in the development kit with thefollowing features: • High (480-Mbps) or full (12-Mb...
CY7C68033/CY7C68034 Document #: 001-04247 Rev. *D Page 3 of 33 Figure 1. Example DVB Block Diagram Figure 2. Example GPS Block Diagram The “Reference Designs” section of the Cypress web siteprovides additional tools for typical USB 2.0 applications. Eachreference design comes complete with firmware ...
CY7C68033/CY7C68034 Document #: 001-04247 Rev. *D Page 6 of 33 If Autovectoring is enabled (AV2EN = 1 in the INTSET-UPregister), the NX2LP-Flex substitutes its INT2VEC byte.Therefore, if the high byte (‘page’) of a jump-table address ispreloaded at location 0x544, the automatically-insertedINT2VEC b...
