Cypress CY7C67200 - Manual

CY7C67200 Document #: 38-08014 Rev. *G Page 5 of 78 Host Port Interface (HPI) EZ-OTG has an HPI interface. The HPI interface providesDMA access to the EZ-OTG internal memory by an externalhost, plus a bidirectional mailbox register for supportinghigh-level communication protocols. This port is desig...

CY7C67200 Document #: 38-08014 Rev. *G Page 7 of 78 Crystal Pins Boot Configuration Interface EZ-OTG can boot into any one of four modes. The mode itboots into is determined by the TTL voltage level ofGPIO[31:30] at the time nRESET is deasserted. Table 14 shows the different boot pin combinations po...

CY7C67200 Document #: 38-08014 Rev. *G Page 8 of 78 Minimum Hardware Requirements for Standalone Mode – Peripheral Only Power Savings and Reset Description The EZ-OTG modes and reset conditions are described in thissection. Power Savings Mode Description EZ-OTG has one main power savings mode, Sleep...

CY7C67200 Document #: 38-08014 Rev. *G Page 9 of 78 External (Remote) Wakeup Source There are several possible events available to wake EZ-OTGfrom Sleep mode as shown in Table 15 . These may also be used as remote wakeup options for USB applications. See section “Power Control Register [0xC00A] [R/W...

CY7C67200 Document #: 38-08014 Rev. *G Page 10 of 78 Registers Some registers have different functions for a read vs. a writeaccess or USB host vs. USB device mode. Therefore,registers of this type have multiple definitions for the sameaddress. The default register values listed in this data sheet m...

CY7C67200 Document #: 38-08014 Rev. *G Page 11 of 78 Bank Register [0xC002] [R/W] Figure 8. Bank Register Register Description The Bank register maps registers R0–R15 into RAM. Theeleven MSBs of this register are used as a base address forregisters R0–R15. A register address is automaticallygenerate...

CY7C67200 Document #: 38-08014 Rev. *G Page 12 of 78 CPU Speed Register [0xC008] [R/W] Figure 10. CPU Speed Register Register Description The CPU Speed register allows the processor to operate at a user selected speed. This register only affects the CPU; all otherperipheral timing is still based on ...

CY7C67200 Document #: 38-08014 Rev. *G Page 23 of 78 ACK Flag (Bit 0) The ACK Flag bit indicates two different conditions dependingon the transfer type. For non-Isochronous transfers, this bitrepresents a transaction ending by receiving or sending anACK packet. For Isochronous transfers, this bit re...

CY7C67200 Document #: 38-08014 Rev. *G Page 24 of 78 Host n Count Result Register [R] • Host 1 Count Result Register 0xC088 • Host 2 Count Result Register 0xC0A8 Figure 23. Host n Count Result Register Register Description The Host n Count Result register is a read-only register thatcontains the siz...

CY7C67200 Document #: 38-08014 Rev. *G Page 48 of 78 HSS Transmit Address Register [0xC07C] [R/W] Figure 54. HSS Transmit Address Register Register Description The HSS Transmit Address register is used as the base pointer address for the next HSS block transmit transfer. Address (Bits [15:0]) The Ad...

CY7C67200 Document #: 38-08014 Rev. *G Page 49 of 78 HPI Breakpoint Register [0x0140] [R] Figure 56. HPI Breakpoint Register Register Description The HPI Breakpoint register is a special on-chip memory location, which the external processor can access using normal HPImemory read/write cycles. This r...

CY7C67200 Document #: 38-08014 Rev. *G Page 56 of 78 Receive Bit Length (Bits [2:0]) The Receive Bit Length field controls whether a full byte or partial byte will be received. If Receive Bit Length is ‘000’ then a fullbyte will be received. If Receive Bit Length is ‘001’ to ‘111’, then the value in...

CY7C67200 Document #: 38-08014 Rev. *G Page 62 of 78 Receive Full (Bit 1) The Receive Full bit indicates whether the receive buffer is full.It can be programmed to interrupt the CPU as interrupt #5when the buffer is full. This can be done though the UART bitof the Interrupt Enable register (0xC00E)....

CY7C67200 Document #: 38-08014 Rev. *G Page 63 of 78 Pin Diagram The following describes the CY7C67200 48-pin FBGA. Figure 76. EZ-OTG Pin Diagram Pin Descriptions Table 38.Pin Descriptions Pin Name Type Description H3 GPIO31/SCK IO GPIO31: General Purpose IO SCK: I2C EEPROM SCK F3 GPIO30/SDA IO GPIO...

CY7C67200 Document #: 38-08014 Rev. *G Page 65 of 78 Absolute Maximum Ratings This section lists the absolute maximum ratings. Stresses above those listed can cause permanent damage to the device.Exposure to maximum rated conditions for extended periods can affect device operation and reliability. S...

CY7C67200 Document #: 38-08014 Rev. *G Page 66 of 78 DC Characteristics Notes 6. All tests were conducted with Charge pump off.7. I CC and I CCB values are the same regardless of USB host or peripheral configuration. 8. There is no appreciable difference in I CC and I CCB values when only one transc...

CY7C67200 Document #: 38-08014 Rev. *G Page 67 of 78 USB Transceiver USB 2.0-compatible in full- and low-speed modes. This product was tested as compliant to the USB-IF specification under the test identification number (TID) of 100390449 and islisted on the USB-IF’s integrators list. AC Timing Char...

CY7C67200 Document #: 38-08014 Rev. *G Page 68 of 78 Clock Timing I 2 C EEPROM Timing Parameter Description Min. Typ. Max. Unit f CLK Clock Frequency 12.0 MHz v XINH [10] Clock Input High(XTALOUT left floating) 1.5 3.0 3.6 V t CLK Clock Period 83.17 83.33 83.5 ns t HIGH Clock High Time 36 44 ns t LO...

CY7C67200 Document #: 38-08014 Rev. *G Page 69 of 78 HPI (Host Port Interface) Write Cycle Timing Note 11. T = system clock period = 1/48 MHz. Parameter Description Min. Typical Max. Unit t ASU Address Setup –1 ns t AH Address Hold –1 ns t CSSU Chip Select Setup –1 ns t CSH Chip Select Hold –1 ns t ...

CY7C67200 Document #: 38-08014 Rev. *G Page 71 of 78 HSS BYTE Mode Transmit qt_clk, CPU_A, CPUHSS_cs, CPU_wr are internal signals, included in the diagram to illustrate relationship between CPU opera-tions and HSS port operations. Bit 0 is LSB of data byte. Data bits are HIGH true: HSS_TxD HIGH = da...

CY7C67200 Document #: 38-08014 Rev. *G Page 72 of 78 Hardware CTS/RTS Handshake t CTSset-up : HSS_CTS setup time before HSS_RTS = 1.5T min. t CTShold : HSS_CTS hold time after START bit = 0 ns min. T = 1/48 MHz. When RTS/CTS hardware handshake is enabled, transmission can be held off by deasserting ...

CY7C67200 Document #: 38-08014 Rev. *G Page 73 of 78 Register Summary Table 42. Register Summary R/W Address Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default High Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Low R 0x0140 HPI Breakpoint Address... 0000 0000 ...Address...

CY7C67200 Document #: 38-08014 Rev. *G Page 77 of 78 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the useof any circuitry other than circuitry embodied in a Cypress pro...

CY7C67200 Document #: 38-08014 Rev. *G Page 78 of 78 Document History Page Document Title: CY7C67200 EZ-OTG™ Programmable USB On-The-Go Host/Peripheral ControllerDocument Number: 38-08014 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 111872 03/22/02 MUL New Data Sheet *A 116988 08...