Cypress CY7C656xx - Manual

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Page 2 – PRELIMINARY; Block Diagrams
Page 4 – Hub Repeater; Applications; System Initialization
Page 5 – Upstream Port; Table 5-1. Automatic Port State to Port Indicator Color Mapping
Page 6 – Table 5-2. Port Indicator Color Definitions in Manual Mode
Page 7 – Pin Configuration
Page 8 – Pin Description Table; Table 7-1 below displays the pin assignments.
Page 9 – Input
Page 10 – Default Descriptors; Device Descriptor
Page 11 – Endpoint Descriptor
Page 12 – Hub Descriptor; Configuration Options; Default – 0xD0 Load
Page 13 – Configured – 0xD2 Load; Byte 10: HubControllerPower; Configured – 0xD4 Load; Byte
Page 14 – Byte 16: PowerOnTimer
Page 15 – Byte 19: Write Protect
Page 16 – Supported USB Requests; Device Class Commands
Page 17 – Hub Class Commands
Page 19 – Upstream USB Connection; The following is a schematic of the USB upstream connector.; Downstream USB Connections; The following is a schematic of the LED circuitry.; Figure 11-1. USB Upstream Port Connection; Figure 12-1. USB Downstream Port Connection; Figure 13-1. USB Downstream Port Connection
Page 20 – System Block Diagram
Page 21 – Electrical Characteristics; Absolute Maximum Ratings; Serial Peripheral Interface; DC Electrical Characteristics
Page 22 – Ordering Information; Ordering Code; CY7C656xx USB 2.0 4 port Hub Reference Design Kit
Page 23 – Document History Page; Issue Date

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PRELIMINARY

EZ-USB HX2LP™

Low-Power USB 2.0 Hub Controller Family

CY7C656xx

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

CA 95134

•

408-943-2600

Document #: 38-08037 Rev. *D

Revised March 31, 2005

1.0

Features

• USB 2.0 hub controller

• Compliant with the USB 2.0 specification

• Windows



Hardware-quality lab (WHQL)-compliant

• Up to four downstream ports supported

• Supports bus-power and self powered modes

• Single-TT and Multi-TT modes supported

— Single-TT option for low-cost

— Multi-TT option for high performance

• 2-Port

— Single TT option for bus power

• Fit/form/function compatible option with CY7C65640

(TetraHub



)

• Multiple package options

— Space-saving 56 QFN

• Single power supply requirement

— Internal regulator for reduced cost

• Integrated upstream pull-up resistor

• Integrated pull-down resistors for all downstream ports

• Integrated upstream and downstream termination

resistors

• Integrated port status indicator controls

• 24-MHz external crystal (integrated PLL)

• Configurable with external SPI EEPROM

— Vendor ID, Product ID, Device ID (VID/PID/DID)

— Number of active ports

— Number of removable ports

— Maximum power setting for high-speed and full-

speed

— Hub controller power setting

— Power-on timer

— Overcurrent detection mode

— Overcurrent timer

— Enable/Disable overcurrent timer

— Overcurrent pin polarity

— indicator pin polarity

— Compound device

— Enable full-speed only

— Disable port indicators

— Gang power switching

— Enable single-TT mode only

— Self/bus powered compatibility

— Fully configurable string descriptors for multiple

language support

• In-system EEPROM programming

2.0

Introduction

EZ-USB HX2LP



is Cypress’s next-generation family of high-

performance, low-power USB 2.0 hub controllers. HX2LP is an
ultra low-power single-chip USB 2.0 hub controller with
integrated upstream and downstream transceivers, a USB
Serial Interface Engine (SIE), USB Hub Control and Repeater
logic, and Transaction Translator (TT) logic. Cypress has also
integrated many of the external passive components, such as
pull-up and pull-down resistors, reducing the overall bill-of-
materials required to implement a hub design. The entire
HX2LP portfolio consists of:

1. CY7C65640B (TetraHub LP): 4-port/multiple transaction

translator

This device option is fit/form/function compatible with Cy-
press’s existing CY7C65640 device. Cypress’s “Tetra” ar-
chitecture provides four downstream USB ports, each with
a dedicated Transaction Translator (TT), making it the high-
est-performance hub available. The TetraHub LP also of-
fers best-in-class power consumption. The CY7C65640B is
available in a 56 QFN (TetraHub pin-compatible) for space
saving designs.

2. CY7C65630: 4-port/single transaction translator

This device option is for ultra low-cost applications where
performance is secondary consideration. All four ports
must share a single transaction translator in this configura-
tion. The CY7C65630 is available in a 56 QFN and is also
pin for pin-compatible with the CY7C65640.

3. CY7C65620:

This device option is for a 2-port bus powered application.
Both ports must share a single transaction translator in this
configuration. The CY7C65620 is available in a 56 QFN
and is also pin for pin compatible with the CY7C65640.

All device options are supported by Cypress’s world-class
reference design kits, which include board schematics, bill of
materials, Gerber files, Orcad files, and thorough design
documentation.

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Summary

Page 2 - PRELIMINARY; Block Diagrams

CY7C656xx PRELIMINARY Document #: 38-08037 Rev. *D Page 2 of 23 3.0 Block Diagrams Figure 3-1. CY7C65640B Block Diagram R o u t i n g L o g i c H ub R epeater U SB U ps tr eam Por t U SB 2.0 PH Y PLL Ser i al Inter face Engi ne H i gh- Speed U SB C ontr ol Logi c SPI C om m uni cati on Bl oc k U SB ...

Page 4 - Hub Repeater; Applications; System Initialization

CY7C656xx PRELIMINARY Document #: 38-08037 Rev. *D Page 4 of 23 3.1 USB Serial Interface Engine (SIE) The SIE allows the CY7C656xx to communicate with the USBhost through the USB repeater component of the HUB. TheSIE handles the following USB activity independently of theHUB Control Block: • Bit stu...

Page 5 - Upstream Port; Table 5-1. Automatic Port State to Port Indicator Color Mapping

CY7C656xx PRELIMINARY Document #: 38-08037 Rev. *D Page 5 of 23 unpowered state. Once the hubs are configured, the ports arenot driven, and the host may power the ports by sending aSetPortPower command to each port. After a port is powered,any connect or disconnect event is detected by the hub. Anyc...