Page 2 - TABLE OF CONTENTS
CY7C64013C CY7C64113C Document #: 38-08001 Rev. *B Page 2 of 51 TABLE OF CONTENTS 1.0 FEATURES .......................................................................................................................................62.0 FUNCTIONAL OVERVIEW ................................................
Page 3 - CC; SWITCHING CHARACTERISTICS
CY7C64013C CY7C64113C Document #: 38-08001 Rev. *B Page 3 of 51 TABLE OF CONTENTS 16.6 DAC Interrupt ..........................................................................................................................3116.7 GPIO/HAPI Interrupt .....................................................
Page 4 - LIST OF FIGURES
CY7C64013C CY7C64113C Document #: 38-08001 Rev. *B Page 4 of 51 LIST OF FIGURES Figure 6-1. Clock Oscillator On-Chip Circuit .......................................................................................... 17Figure 7-1. Watchdog Reset (WDR) ....................................................
Page 5 - LIST OF TABLES
CY7C64013C CY7C64113C Document #: 38-08001 Rev. *B Page 5 of 51 LIST OF TABLES Table 4-1. Pin Assignments ..................................................................................................................10Table 4-2. I/O Register Summary .................................................
Page 6 - Features
CY7C64013C CY7C64113C Document #: 38-08001 Rev. *B Page 6 of 51 1.0 Features • Full-speed USB Microcontroller• 8-bit USB Optimized Microcontroller — Harvard architecture— 6-MHz external clock source— 12-MHz internal CPU clock— 48-MHz internal clock • Internal memory — 256 bytes of RAM— 8 KB of PROM ...
Page 7 - Functional Overview; for a variety of non-USB embedded applications.
CY7C64013C CY7C64113C Document #: 38-08001 Rev. *B Page 7 of 51 2.0 Functional Overview The CY7C64013C and CY7C64113C are 8-bit One Time Programmable microcontrollers that are designed for full-speed USB applications. The instruction set has been optimized specifically for USB operations, although t...
Page 8 - Logic Block Diagram; bit
CY7C64013C CY7C64113C Document #: 38-08001 Rev. *B Page 8 of 51 Logic Block Diagram Interrupt Controller PROM 12-bit Timer Reset Watchdog Timer Power-On SCLK I 2 C GPIO PORT 1 GPIO PORT 0 P0[7:0] P1[2:0] P1[7:3] SDATA 8- bit B u s 6-MHz crystal RAM USB SIE USB Transceiver D+[0]D–[0] Upstream USB Por...
Page 9 - Pin Configurations; TOP VIEW
CY7C64013C CY7C64113C Document #: 38-08001 Rev. *B Page 9 of 51 3.0 Pin Configurations 1 2 3 4 5 6 7 9 11 12 13 14 15 16 18 17 XTALIN 10 8 19 20 31 30 29 33 32 35 34 37 36 39 38 41 40 43 42 45 44 46 48 47 21 22 23 24 25 27 26 28 V CC P1[1] P1[0] P1[2] P1[4] P1[6] P3[0] P3[2] V REF P1[3] P1[5] P1[7] ...
Page 10 - Product Summary Tables; Pin Assignments; Name; Register Name
CY7C64013C CY7C64113C Document #: 38-08001 Rev. *B Page 10 of 51 4.0 Product Summary Tables 4.1 Pin Assignments 4.2 I/O Register Summary I/O registers are accessed via the I/O Read (IORD) and I/O Write (IOWR, IOWX) instructions. IORD reads data from the selected port into the accumulator. IOWR perfo...
Page 12 - Instruction Set Summary; CYASM Assembler User’s Guide
CY7C64013C CY7C64113C Document #: 38-08001 Rev. *B Page 12 of 51 4.3 Instruction Set Summary Refer to the CYASM Assembler User’s Guide for more details. Table 4-3. Instruction Set Summary MNEMONIC operand opcode cycles MNEMONIC operand opcode cycles HALT 00 7 NOP 20 4 ADD A,expr data 01 4 INC A acc ...
Page 13 - Programming Model; location 0x00 and up.
CY7C64013C CY7C64113C Document #: 38-08001 Rev. *B Page 13 of 51 5.0 Programming Model 5.1 14-Bit Program Counter (PC) The 14-bit program counter (PC) allows access to up to 8 KB of PROM available with the CY7C64x13C architecture. The top 32 bytes of the ROM in the 8 Kb part are reserved for testing...
Page 14 - Program Memory Organization; Program Memory begins here
CY7C64013C CY7C64113C Document #: 38-08001 Rev. *B Page 14 of 51 5.1.1 Program Memory Organization after reset Address 14-bit PC 0x0000 Program execution begins here after a reset 0x0002 USB Bus Reset interrupt vector 0x0004 128-µs timer interrupt vector 0x0006 1.024-ms timer interrupt vector 0x0008...
Page 15 - Program Stack Growth; user selected; Data Stack Growth
CY7C64013C CY7C64113C Document #: 38-08001 Rev. *B Page 15 of 51 5.2 8-Bit Accumulator (A) The accumulator is the general-purpose register for the microcontroller. 5.3 8-Bit Temporary Register (X) The “X” register is available to the firmware for temporary storage of intermediate results. The microc...
Page 16 - SWAP A,DSP swap accumulator value into DSP register; Address Modes; instruction that loads A with the constant 0xD8:
CY7C64013C CY7C64113C Document #: 38-08001 Rev. *B Page 16 of 51 5.5 8-Bit Data Stack Pointer (DSP) The data stack pointer (DSP) supports PUSH and POP instructions that use the data stack for temporary storage. A PUSH instruction pre-decrements the DSP, then writes data to the memory location addres...
Page 17 - XTALOUT
CY7C64013C CY7C64113C Document #: 38-08001 Rev. *B Page 17 of 51 6.0 Clocking The XTALIN and XTALOUT are the clock pins to the microcontroller. The user can connect an external oscillator or a crystal to these pins. When using an external crystal, keep PCB traces between the chip leads and crystal a...
Page 18 - Suspend Mode; Last write to
CY7C64013C CY7C64113C Document #: 38-08001 Rev. *B Page 18 of 51 The USB transmitter is disabled by a Watchdog Reset because the USB Device Address Register is cleared (see Section 18.1). Otherwise, the USB Controller would respond to all address 0 transactions.It is possible for the WDR bit of the ...
Page 19 - through
CY7C64013C CY7C64113C Document #: 38-08001 Rev. *B Page 19 of 51 9.0 General-Purpose I/O (GPIO) Ports There are up to 32 GPIO pins (P0[7:0], P1[7:0], P2[7:0], and P3[7:0]) for the hardware interface. The number of GPIO pins changes based on the package type of the chip. Each port can be configured a...
Page 20 - GPIO Configuration Port; Interrupt Polarity
CY7C64013C CY7C64113C Document #: 38-08001 Rev. *B Page 20 of 51 Port 3 Data ADDRESS 0x03 Special care should be taken with any unused GPIO data bits. An unused GPIO data bit, either a pin on the chip or a port bit that is not bonded on a particular package, must not be left floating when the device...
Page 21 - GPIO Interrupt Enable Ports; DAC Port
CY7C64013C CY7C64113C Document #: 38-08001 Rev. *B Page 21 of 51 Q1, Q2, and Q3 discussed below are the transistors referenced in Figure 9-1 . The available GPIO drive strength are: • Output LOW Mode: The pin’s Data Register is set to ‘0’ Writing ‘0’ to the pin’s Data Register puts the pin in output...
Page 22 - ) is set, the Isink DAC block of the DAC circuitry; DAC Isink Registers; DAC
CY7C64013C CY7C64113C Document #: 38-08001 Rev. *B Page 22 of 51 The amount of sink current for the DAC I/O pin is programmable over 16 values based on the contents of the DAC Isink Register for that output pin. DAC[1:0] are high-current outputs that are programmable from 3.2 mA to 16 mA (typical). ...
Page 23 - spaced between these two values.; DAC Port Interrupts; cleared during a reset.
CY7C64013C CY7C64113C Document #: 38-08001 Rev. *B Page 23 of 51 Bit [4..0]: Isink [x] (x= 0..4) Writing all ‘0’s to the Isink register causes 1/5 of the max current to flow through the DAC I/O pin. Writing all ‘1’s to the Isink register provides the maximum current flow through the pin. The other 1...
Page 24 - C and HAPI Configuration Register; shows the HAPI port configurations, and; C Configuration Register
CY7C64013C CY7C64113C Document #: 38-08001 Rev. *B Page 24 of 51 Timer MSB ADDRESS 0x25 Bit [3:0]: Timer higher nibbleBit [7:4]: Reserved 12.0 I 2 C and HAPI Configuration Register Internal hardware supports communication with external devices through two interfaces: a two-wire I 2 C-compatible inte...
Page 25 - C-compatible Controller
CY7C64013C CY7C64113C Document #: 38-08001 Rev. *B Page 25 of 51 13.0 I 2 C-compatible Controller The I 2 C-compatible block provides a versatile two-wire communication with external devices, supporting master, slave, and multi- master modes of operation. The I 2 C-compatible block functions by hand...
Page 27 - Hardware Assisted Parallel Interface (HAPI)
CY7C64013C CY7C64113C Document #: 38-08001 Rev. *B Page 27 of 51 to the data register before setting the Continue bit. To prevent false ARB Lost signals, the Restart bit is cleared by hardware during the restart sequence. Bit 1 : Receive Stop This bit is set when the slave is in receive mode and det...
Page 28 - Processor Status and Control Register; Bit 2: Interrupt Enable Sense; Figure 15-1. Processor Status and Control Register
CY7C64013C CY7C64113C Document #: 38-08001 Rev. *B Page 28 of 51 15.0 Processor Status and Control Register Processor Status and Control ADDRESS 0xFF Bit 0: Run This bit is manipulated by the HALT instruction. When Halt is executed, all the bits of the Processor Status and Control Register are clear...
Page 29 - Interrupts; C-compatible interface or HAPI operation, or on various
CY7C64013C CY7C64113C Document #: 38-08001 Rev. *B Page 29 of 51 16.0 Interrupts Interrupts are generated by the GPIO/DAC pins, the internal timers, I 2 C-compatible interface or HAPI operation, or on various USB traffic conditions. All interrupts are maskable by the Global Interrupt Enable Register...
Page 30 - Interrupt Vectors; Figure 16-3. Interrupt Controller Function Diagram
CY7C64013C CY7C64113C Document #: 38-08001 Rev. *B Page 30 of 51 The interrupt controller contains a separate flip-flop for each interrupt. See Figure 16-3 for the logic block diagram of the interrupt controller. When an interrupt is generated, it is first registered as a pending interrupt. It stays...
Page 31 - Table 16-1. Interrupt Vector Assignments
CY7C64013C CY7C64113C Document #: 38-08001 Rev. *B Page 31 of 51 16.2 Interrupt Latency Interrupt latency can be calculated from the following equation:Interrupt latency = (Number of clock cycles remaining in the current instruction) + (10 clock cycles for the CALL instruction) + (5 clock cycles for...
Page 32 - C Interrupt; slave receive
CY7C64013C CY7C64113C Document #: 38-08001 Rev. *B Page 32 of 51 16.7 GPIO/HAPI Interrupt Each of the GPIO pins can generate an interrupt, if enabled. The interrupt polarity can be programmed for each GPIO port as part of the GPIO configuration. All of the GPIO pins share a single interrupt vector, ...
Page 33 - master receive; ACK; USB Overview; USB Enumeration
CY7C64013C CY7C64113C Document #: 38-08001 Rev. *B Page 33 of 51 5. In master receive mode, after the master receives a byte of data: Firmware should read the data and set the ACK and Continue/Busy bits appropriately for the next byte. Clearing the MSTR MODE bit at the same time causes the master st...
Page 34 - USB Serial Interface Engine Operation; USB Device Address
CY7C64013C CY7C64113C Document #: 38-08001 Rev. *B Page 34 of 51 USB Status and Control ADDRESS 0x1F Bits[2..0] : Control Action Set to control action as per Table 17-1 .The three control bits allow the upstream port to be driven manually by firmware. For normal USB operation, all of these bits must...
Page 35 - USB Device Endpoints; Table; USB Control Endpoint Mode Register; unused
CY7C64013C CY7C64113C Document #: 38-08001 Rev. *B Page 35 of 51 Bits[6..0] :Device Address Firmware writes this bits during the USB enumeration process to the non-zero address assigned by the USB host. Bit 7 :Device Address Enable Must be set by firmware before the SIE can respond to USB traffic to...
Page 36 - for the appropriate endpoint zero; USB Non-Control Endpoint Mode Registers; The format of the non-control endpoint mode register is shown in; Must be written zero during register writes.; USB Endpoint Counter Registers; in; Figure 18-4. USB Endpoint Counter Registers
CY7C64013C CY7C64113C Document #: 38-08001 Rev. *B Page 36 of 51 Bit 6: Endpoint 0 IN Received 1= Token received is an IN token. 0= Token received is not an IN token. This bit is set by the SIE to report the type of token received by the corresponding device address is an IN token. The bit must be c...
Page 37 - Endpoint Mode/Count Registers Update and Locking Mechanism; register which was locked earlier.
CY7C64013C CY7C64113C Document #: 38-08001 Rev. *B Page 37 of 51 Bits[5..0] : Byte Count These counter bits indicate the number of data bytes in a transaction. For IN transactions, firmware loads the count with the number of bytes to be transmitted to the host from the endpoint FIFO. Valid values ar...
Page 39 - USB Mode Tables
CY7C64013C CY7C64113C Document #: 38-08001 Rev. *B Page 39 of 51 19.0 USB Mode Tables Mode This lists the mnemonic given to the different modes that can be set in the Endpoint Mode Register by writing to the lower nibble (bits 0..3). The bit settings for different modes are covered in the column mar...
Page 40 - Comments; the SIE to respond appropriately. See
CY7C64013C CY7C64113C Document #: 38-08001 Rev. *B Page 40 of 51 An “Accept” in any of the columns means that the device will respond with an ACK to a valid SETUP transaction tot he host. Comments Some Mode Bits are automatically changed by the SIE in response to certain USB transactions. For exampl...
Page 41 - Table 19-2. Details of Modes for Differing Traffic Conditions; for the decode legend)
CY7C64013C CY7C64113C Document #: 38-08001 Rev. *B Page 41 of 51 the firmware recognizes the changes that the SIE might have made during the previous transaction. Note that the setup bit of the mode register is NOT locked. This means that before writing to the mode register, firmware must first read...
Page 43 - Register Summary; Address Register Name Bit 7
CY7C64013C CY7C64113C Document #: 38-08001 Rev. *B Page 43 of 51 20.0 Register Summary Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read/Write/ Both/- Default/ Reset GP IO C O N F IG URA TION P O RTS 0, 1 , 2 AND 3 0x00 Port 0 Data P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 BBB...
Page 44 - Sample Schematic; SHELL
CY7C64013C CY7C64113C Document #: 38-08001 Rev. *B Page 44 of 51 Note: B: Read and WriteW: WriteR: Read 21.0 Sample Schematic RE SER VE D 0x48 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 00000000 0x49 Reserved Reserved Reserved Reserved Reserved Reserved...
Page 46 - Switching Characteristics; Electrical Characteristics
CY7C64013C CY7C64113C Document #: 38-08001 Rev. *B Page 46 of 51 DAC Interface R up DAC Pull-up Resistance (typical 14 k Ω) 8.0 24.0 k Ω I sink0(0) DAC[7:2] Sink current (0) V out = 2.0V DC 0.1 0.3 mA I sink0(F) DAC[7:2] Sink current (F) V out = 2.0V DC 0.5 1.5 mA I sink1(0) DAC[1:0] Sink current (0...
Page 47 - Internal Write
CY7C64013C CY7C64113C Document #: 38-08001 Rev. *B Page 47 of 51 Figure 24-1. Clock Timing Figure 24-2. USB Data Signal Timing Figure 24-3. HAPI Read by External Interface from USB Microcontroller CLOCK t CYC t CL t CH 90% 10% 90% 10% D − D + t r t r OE (P2.5, input) DATA (output) STB (P2.4, input) ...
Page 48 - Ordering Information; Commercial; Internal Read; Int
CY7C64013C CY7C64113C Document #: 38-08001 Rev. *B Page 48 of 51 25.0 Ordering Information Ordering Code PROM Size Package Type Operating Range CY7C64013C-SXC 8 KB 28-Pin (300-Mil) SOIC Commercial CY7C64013C-PXC 8 KB 28-Pin (300-Mil) PDIP Commercial CY7C64013C-SXCT 8 KB 28-Pin (300-Mil) SOIC - Tape ...
Page 49 - Package Diagrams; 8-Lead Shrunk Small Outline Package
CY7C64013C CY7C64113C Document #: 38-08001 Rev. *B Page 49 of 51 26.0 Package Diagrams 48-Lead Shrunk Small Outline Package 51-85061-*C DIMENSIONS IN INCHES [MM] MIN. MAX. SEATING PLANE 0.260[6.60]0.295[7.49] 0.090[2.28] 0.110[2.79] 0.055[1.39]0.065[1.65] 0.015[0.38]0.020[0.50] 0.015[0.38]0.060[1.52...
Page 51 - Document History Page; Issue
CY7C64013C CY7C64113C Document #: 38-08001 Rev. *B Page 51 of 51 Document History Page Document Title: CY7C64013C, CY7C64113C Full-Speed USB (12 Mbps) Function Document Number: 38-08001 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 109962 12/16/01 SZV Change from Spec number: 38-0...
