Cypress CY7C1917CV18 - Manual
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Table of Contents:
- Page 4 – Pin Configuration
- Page 6 – Pin Definitions; Application Example
- Page 8 – Functional Overview; Read Operations; Write Operations; Single Clock Mode
- Page 9 – to enable the SRAM to adjust its output; Echo Clocks; Switching; DLL; DLL Considerations in QDRIITM/DDRII
- Page 10 – Figure 1; Truth Table; ohms; BUS
- Page 11 – Burst Address Table
- Page 12 – BWS
- Page 13 – Disabling the JTAG Feature; Test Access Port—Test Clock; TAP Registers; Instruction Register; Boundary Scan Register; TAP Instruction Set
- Page 14 – and t; ). The SRAM clock input might not be captured
- Page 15 – TAP Controller State Diagram; The state diagram for the TAP controller follows.; RESET
- Page 17 – Figure 2
- Page 19 – Boundary Scan Order; Bump ID; Internal
- Page 20 – Power Up Sequence in DDR-II SRAM; Power Up Sequence; Figure 3. Power Up Waveforms
- Page 21 – Maximum Ratings; Operating Range; DC Electrical Characteristics
- Page 22 – AC Electrical Characteristics
- Page 23 – Capacitance; Thermal Resistance
- Page 24 – Switching Characteristics
- Page 26 – Switching Waveforms; DON’T CARE
- Page 27 – Ordering Information; for actual products offered.
- Page 30 – Package Diagram
- Page 31 – Document History Page; Submission
18-Mbit DDR-II SRAM 4-Word
Burst Architecture
CY7C1317CV18, CY7C1917CV18
CY7C1319CV18, CY7C1321CV18
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document Number: 001-07161 Rev. *D
Revised June 18, 2008
Features
■
18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36)
■
300 MHz clock for high bandwidth
■
4-word burst for reducing address bus frequency
■
Double Data Rate (DDR) interfaces
(data transferred at 600 MHz) at 300 MHz
■
Two input clocks (K and K) for precise DDR timing
❐
SRAM uses rising edges only
■
Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
■
Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
■
Synchronous internally self-timed writes
■
DDR-II operates with 1.5 cycle read latency when the DLL is
enabled
■
Operates similar to a DDR-I device with 1 cycle read latency in
DLL off mode
■
1.8V core power supply with HSTL inputs and outputs
■
Variable drive HSTL output buffers
■
Expanded HSTL output voltage (1.4V–V
DD
)
■
Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)
■
Offered in both Pb-free and non Pb-free packages
■
JTAG 1149.1 compatible test access port
■
Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1317CV18 – 2M x 8
CY7C1917CV18 – 2M x 9
CY7C1319CV18 – 1M x 18
CY7C1321CV18 – 512K x 36
Functional Description
The CY7C1317CV18, CY7C1917CV18, CY7C1319CV18, and
CY7C1321CV18 are 1.8V Synchronous Pipelined SRAMs
equipped with DDR-II architecture. The DDR-II consists of an
SRAM core with advanced synchronous peripheral circuitry and
a two-bit burst counter. Addresses for read and write are latched
on alternate rising edges of the input (K) clock. Write data is
registered on the rising edges of both K and K. Read data is
driven on the rising edges of C and C if provided, or on the rising
edge of K and K if C/C are not provided. Each address location
is associated with four 8-bit words in the case of CY7C1317CV18
and four 9-bit words in the case of CY7C1917CV18 that burst
sequentially into or out of the device. The burst counter always
starts with a ‘00’ internally in the case of CY7C1317CV18 and
CY7C1917CV18. For CY7C1319CV18 and CY7C1321CV18,
the burst counter takes in the least two significant bits of the
external address and bursts four 18-bit words in the case of
CY7C1319CV18, and four 36-bit words in the case of
CY7C1321CV18, sequentially into or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs, D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need to capture data
separately from each individual DDR SRAM in the system
design. Output data clocks (C/C) enable maximum system
clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Selection Guide
Description
300 MHz
278 MHz
250 MHz
200 MHz
167 MHz
Unit
Maximum Operating Frequency
300
278
250
200
167
MHz
Maximum Operating Current
x8
770
720
670
580
515
mA
x9
770
720
670
580
515
x18
810
760
700
600
540
x36
890
830
765
655
600
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Summary
CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev. *D Page 4 of 31 Pin Configuration The pin configuration for CY7C1317CV18, CY7C1917CV18, CY7C1319CV18, and CY7C1321CV18 follow. [1] 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1317CV18 (2M x 8) 1 2 3 4 5 6 7 8 9 10 1...
CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev. *D Page 6 of 31 Pin Definitions Pin Name IO Pin Description DQ [x:0] Input Output-Synchronous Data Input Output Signals . Inputs are sampled on the rising edge of K and K clocks during valid write operations. These ...
CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev. *D Page 8 of 31 Functional Overview The CY7C1317CV18, CY7C1917CV18, CY7C1319CV18, andCY7C1321CV18 are synchronous pipelined Burst SRAMsequipped with a DDR interface, which operates with a readlatency of one and half...
