Cypress CY7C1557V18 - Manual
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Table of Contents:
- Page 2 – Array; Array
- Page 3 – ray
- Page 4 – Pin Configuration
- Page 6 – Pin Definitions; Switching Characteristics
- Page 8 – Functional Overview; Write Operations
- Page 9 – Echo Clocks; DLL; Application Example; Figure 1; Figure 1. Application Example; BUS; DQ
- Page 10 – Truth Table
- Page 12 – Disabling the JTAG Feature; Test Access Port—Test Clock; TAP Registers; Instruction Register; Boundary Scan Register; TAP Instruction Set
- Page 13 – and t; ). The SRAM clock input might not be captured
- Page 14 – TAP Controller State Diagram; The state diagram for the TAP controller follows.; RESET
- Page 18 – Boundary Scan Order; Internal
- Page 19 – Power Up Waveforms; Figure 3. Power Up Waveforms; DOFF; Unstable Clock
- Page 20 – Maximum Ratings; Operating Range; DC Electrical Characteristics
- Page 21 – AC Electrical Characteristics; Capacitance
- Page 22 – Figure 4. AC Test Loads and Waveforms; ZQ
- Page 24 – Switching Waveforms; Figure 5. Waveform for 2.0 Cycle Read Latency; DON’T CARE; t CQD
- Page 25 – Ordering Information; for actual products offered.
- Page 27 – Package Diagram
- Page 28 – Document History Page; Issue
72-Mbit DDR-II+ SRAM 2-Word Burst
Architecture (2.0 Cycle Read Latency)
CY7C1546V18, CY7C1557V18
CY7C1548V18, CY7C1550V18
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document Number: 001-06550 Rev. *E
Revised March 11, 2008
Features
■
72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36)
■
375 MHz clock for high bandwidth
■
2-word burst for reducing address bus frequency
■
Double Data Rate (DDR) interfaces
(data transferred at 750 MHz) at 375 MHz
■
Available in 2.0 clock cycle latency
■
Two input clocks (K and K) for precise DDR timing
❐
SRAM uses rising edges only
■
Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
■
Data valid pin (QVLD) to indicate valid data on the output
■
Synchronous internally self-timed writes
■
Core V
DD
= 1.8V ± 0.1V; IO V
DDQ
= 1.4V to V
DD
■
HSTL inputs and variable drive HSTL output buffers
■
Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)
■
Offered in both Pb-free and non Pb-free packages
■
JTAG 1149.1 compatible test access port
■
Delay Lock Loop (DLL) for accurate data placement
Configurations
With Read Cycle Latency of 2.0 cycles:
CY7C1546V18 – 8M x 8
CY7C1557V18 – 8M x 9
CY7C1548V18 – 4M x 18
CY7C1550V18 – 2M x 36
Functional Description
The CY7C1546V18, CY7C1557V18, CY7C1548V18, and
CY7C1550V18 are 1.8V Synchronous Pipelined SRAM
equipped with DDR-II+ architecture. The DDR-II+ consists of an
SRAM core with advanced synchronous peripheral circuitry.
Addresses for read and write are latched on alternate rising
edges of the input (K) clock. Write data is registered on the rising
edges of both K and K. Read data is driven on the rising edges
of both K and K. Each address location is associated with two
8-bit words (CY7C1546V18), 9-bit words (CY7C1557V18),
18-bit words (CY7C1548V18), or 36-bit words (CY7C1550V18)
that burst sequentially into or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs, D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Selection Guide
Description
375 MHz
333 MHz
300 MHz
Unit
Maximum Operating Frequency
375
333
300
MHz
Maximum Operating Current
x8
1300
1200
1100
mA
x9
1300
1200
1100
x18
1300
1200
1100
x36
1300
1200
1100
Note
1. The QDR consortium specification for V
DDQ
is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting V
DDQ
= 1.4V to V
DD
.
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Summary
CY7C1546V18, CY7C1557V18CY7C1548V18, CY7C1550V18 Document Number: 001-06550 Rev. *E Page 2 of 28 Logic Block Diagram (CY7C1546V18) Logic Block Diagram (CY7C1557V18) CLK A (21:0) Gen. K K Control Logic Address Register R ead Add. Decode Read Data Reg. R/W DQ [7:0] Output Logic Reg. Reg. Reg. 8 8 16 8...
CY7C1546V18, CY7C1557V18CY7C1548V18, CY7C1550V18 Document Number: 001-06550 Rev. *E Page 3 of 28 Logic Block Diagram (CY7C1548V18) Logic Block Diagram (CY7C1550V18) CLK A (20:0) Gen. K K Control Logic Address Register R ead Add. Decode Read Data Reg. R/W DQ [17:0] Output Logic Reg. Reg. Reg. 18 18 3...
CY7C1546V18, CY7C1557V18CY7C1548V18, CY7C1550V18 Document Number: 001-06550 Rev. *E Page 4 of 28 Pin Configuration The pin configuration for CY7C1546V18, CY7C1557V18, CY7C1548V18, and CY7C1550V18 follow. [2] 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1546V18 (8M x 8) 1 2 3 4 5 6 7 8 9 10 11 A CQ A ...
