Cypress CY7C1518AV18 - Manual
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Table of Contents:
- Page 2 – rray
- Page 4 – Pin Configuration
- Page 6 – Pin Definitions
- Page 8 – Functional Overview; Read Operations; Write Operations; Single Clock Mode
- Page 9 – to allow the SRAM to adjust its output; Echo Clocks; Switching Characteristics; DLL; DLL Considerations in QDRIITM/DDRII; Application Example; Figure 1; Figure 1. Application Example; ohms; BUS
- Page 10 – Write Cycle Descriptions
- Page 12 – Disabling the JTAG Feature; Test Access Port—Test Clock; TAP Registers; Instruction Register; Boundary Scan Register; TAP Instruction Set
- Page 13 – and t; ). The SRAM clock input might not be captured
- Page 14 – TAP Controller State Diagram; The state diagram for the TAP controller follows.; RESET
- Page 16 – Figure 2
- Page 18 – Boundary Scan Order; Bump ID; Internal
- Page 19 – Power Up Sequence in DDR-II SRAM; Power Up Sequence; Figure 3. Power Up Waveforms
- Page 20 – Maximum Ratings; Operating Range; DC Electrical Characteristics
- Page 21 – AC Electrical Characteristics
- Page 22 – Capacitance; Thermal Resistance
- Page 25 – Switching Waveforms; LD; CQD
- Page 26 – Ordering Information; for actual products offered.
- Page 29 – Package Diagram
- Page 30 – Document History Page; SUBMISSION
72-Mbit DDR-II SRAM 2-Word
Burst Architecture
CY7C1516AV18, CY7C1527AV18
CY7C1518AV18, CY7C1520AV18
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document Number: 001-06982 Rev. *D
Revised June 16, 2008
Features
■
72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36)
■
300 MHz clock for high bandwidth
■
2-word burst for reducing address bus frequency
■
Double Data Rate (DDR) interfaces
(data transferred at 600 MHz) at 300 MHz
■
Two input clocks (K and K) for precise DDR timing
❐
SRAM uses rising edges only
■
Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
■
Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
■
Synchronous internally self-timed writes
■
DDR-II operates with 1.5 cycle read latency when Delay Lock
Loop (DLL) is enabled
■
Operates as a DDR-I device with 1 cycle read latency in DLL
off mode
■
1.8V core power supply with HSTL inputs and outputs
■
Variable drive HSTL output buffers
■
Expanded HSTL output voltage (1.4V–V
DD
)
■
Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)
■
Offered in both Pb-free and non Pb-free packages
■
JTAG 1149.1 compatible test access port
■
Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1516AV18 – 8M x 8
CY7C1527AV18 – 8M x 9
CY7C1518AV18 – 4M x 18
CY7C1520AV18 – 2M x 36
Functional Description
The CY7C1516AV18, CY7C1527AV18, CY7C1518AV18, and
CY7C1520AV18 are 1.8V Synchronous Pipelined SRAM
equipped with DDR-II architecture. The DDR-II consists of an
SRAM core with advanced synchronous peripheral circuitry and
a 1-bit burst counter. Addresses for read and write are latched
on alternate rising edges of the input (K) clock. Write data is
registered on the rising edges of both K and K. Read data is
driven on the rising edges of C and C if provided, or on the rising
edge of K and K if C/C are not provided. Each address location
is associated with two 8-bit words in the case of CY7C1516AV18
and two 9-bit words in the case of CY7C1527AV18 that burst
sequentially into or out of the device. The burst counter always
starts with a “0” internally in the case of CY7C1516AV18 and
CY7C1527AV18. On CY7C1518AV18 and CY7C1520AV18, the
burst counter takes in the least significant bit of the external
address and bursts two 18-bit words in the case of
CY7C1518AV18 and two 36-bit words in the case of
CY7C1520AV18 sequentially into or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design. Output data clocks (C/C) enable maximum system
clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Selection Guide
Description
300 MHz
278 MHz
250 MHz
200 MHz
167 MHz
Unit
Maximum Operating Frequency
300
278
250
200
167
MHz
Maximum Operating Current
x8
900
860
800
700
650
mA
x9
900
860
800
700
650
x18
940
860
800
700
650
x36
1080
985
900
735
650
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Summary
CY7C1516AV18, CY7C1527AV18CY7C1518AV18, CY7C1520AV18 Document Number: 001-06982 Rev. *D Page 2 of 30 Logic Block Diagram (CY7C1516AV18) Logic Block Diagram (CY7C1527AV18) WriteReg WriteReg CLK A (21:0) Gen. K K Control Logic Address Register Read Add . Decode Read Data Reg. R/W Output Logic Reg. Reg...
CY7C1516AV18, CY7C1527AV18CY7C1518AV18, CY7C1520AV18 Document Number: 001-06982 Rev. *D Page 4 of 30 Pin Configuration The pin configuration for CY7C1516AV18, CY7C1527AV18, CY7C1518AV18, and CY7C1520AV18 follow. [1] 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1516AV18 (8M x 8) 1 2 3 4 5 6 7 8 9 10 1...
CY7C1516AV18, CY7C1527AV18CY7C1518AV18, CY7C1520AV18 Document Number: 001-06982 Rev. *D Page 6 of 30 Pin Definitions Pin Name IO Pin Description DQ [x:0] Input Output-Synchronous Data Input Output Signals . Inputs are sampled on the rising edge of K and K clocks during valid write operations. These ...
