Cypress CY7C1470V33 - Manual
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Table of Contents:
- Page 2 – Selection Guide; Unit
- Page 4 – Pin Configurations; TMS
- Page 6 – Pin Definitions
- Page 7 – Functional Overview
- Page 8 – DD; ZZ Mode Electrical Characteristics
- Page 9 – Truth Table
- Page 10 – Partial Write Cycle Description
- Page 11 – Disabling the JTAG Feature; through a pull-up resistor. TDO should be; TAP Controller State Diagram; Performing a TAP Reset; A RESET is performed by forcing TMS HIGH (V; TAP Registers
- Page 12 – ) when the BYPASS instruction is executed.; TAP Instruction Set; plus t
- Page 13 – TAP Timing; Test Clock; TAP AC Switching Characteristics
- Page 14 – Parameter
- Page 18 – Electrical Characteristics
- Page 20 – Switching Characteristics
- Page 21 – Switching Waveforms
- Page 23 – Ordering Information; Commercial
- Page 25 – Package Diagrams
- Page 28 – Document History Page; Issue Date
72-Mbit (2M x 36/4M x 18/1M x 72)
Pipelined SRAM with NoBL™ Architecture
CY7C1470V33
CY7C1472V33
CY7C1474V33
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 38-05289 Rev. *I
Revised June 20, 2006
Features
• Pin-compatible and functionally equivalent to ZBT™
• Supports 250-MHz bus operations with zero wait states
— Available speed grades are 250, 200 and 167 MHz
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write capability
• Single 3.3V power supply
• 3.3V/2.5V I/O power supply
• Fast clock-to-output time
— 3.0 ns (for 250-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• CY7C1470V33, CY7C1472V33 available in
JEDEC-standard lead-free 100-pin TQFP, lead-free and
non-lead-free 165-ball FBGA package. CY7C1474V33
available in lead-free and non-lead-free 209 ball FBGA
package
• IEEE 1149.1 JTAG Boundary Scan compatible
• Burst capability—linear or interleaved burst order
• “ZZ” Sleep Mode option and Stop Clock option
Functional Description
The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are
3.3V, 2M x 36/4M x 18/1M x 72 Synchronous pipelined burst
SRAMs with No Bus Latency™ (NoBL
™)
logic, respectively.
They are designed to support unlimited true back-to-back
Read/Write operations with no wait states. The
CY7C1470V33, CY7C1472V33, and CY7C1474V33 are
equipped with the advanced (NoBL) logic required to enable
consecutive Read/Write operations with data being trans-
ferred on every clock cycle. This feature dramatically improves
the throughput of data in systems that require frequent
Write/Read transitions. The CY7C1470V33, CY7C1472V33,
and CY7C1474V33 are pin compatible and functionally equiv-
alent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which when deasserted suspends operation and extends the
previous clock cycle.
Write operations are controlled by the Byte Write Selects
(BW
a
–BW
h
for CY7C1474V33, BW
a
–BW
d
for CY7C1470V33
and BW
a
–BW
b
for CY7C1472V33) and a Write Enable (WE)
input. All writes are conducted with on-chip synchronous
self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
Logic Block Diagram-CY7C1470V33 (2M x 36)
A0, A1, A
C
MODE
BW
a
BW
b
WE
CE1
CE2
CE3
OE
READ LOGIC
DQs
DQP
a
DQP
b
DQP
c
DQP
d
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
MEMORY
ARRAY
E
E
INPUT
REGISTER 0
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC
A0'
A1'
D1
D0
Q1
Q0
A0
A1
C
ADV/LD
ADV/LD
E
INPUT
REGISTER 1
S
E
N
S
E
A
M
P
S
E
CLK
CEN
WRITE
DRIVERS
BW
c
BW
d
ZZ
SLEEP
CONTROL
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
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Summary
CY7C1470V33CY7C1472V33CY7C1474V33 Document #: 38-05289 Rev. *I Page 2 of 29 A0, A1, A C MODE CE1CE2CE3 OE READ LOGIC DQsDQP a DQP b DQP c DQP d DQP e DQP f DQP g DQP h D A T A S T E E R I N G O U T P U T B U F F E R S MEMORY ARRAY E E INPUT REGISTER 0 ADDRESS REGISTER 0 WRITE ADDRESS REGISTER 1 WRIT...
CY7C1470V33CY7C1472V33CY7C1474V33 Document #: 38-05289 Rev. *I Page 4 of 29 Pin Configurations (continued) 2 3 4 5 6 7 1 A B CD E F G H J K L M N P R TDO NC/576M NC/1G DQP c DQ c DQP d NC DQ d A CE 1 BW b CE 3 BW c CEN A CE2 DQ c DQ d DQ d MODE NC DQ c DQ c DQ d DQ d DQ d A V DDQ BW d BW a CLK WE V ...
CY7C1470V33CY7C1472V33CY7C1474V33 Document #: 38-05289 Rev. *I Page 6 of 29 Pin Definitions Pin Name I/O Type Pin Description A0A1A Input- Synchronous Address Inputs used to select one of the address locations . Sampled at the rising edge of the CLK. BW a BW b BW c BW d BW e BW f BW g BW h Input- Sy...
