Cypress CY7C1399B - Manual
Cypress CY7C1399B – Manual, read for free online in PDF format. We hope this helps you resolve any issues you may have. If you have further questions, please contact us through the contact form.
Table of Contents:
- Page 2 – Top View; Operating Range; Electrical Characteristics
- Page 4 – Switching Characteristics; Parameter
- Page 7 – Switching Waveforms
- Page 8 – Truth Table; Ordering Information
- Page 9 – Package Diagrams
- Page 10 – Revision History; ISSUE DATE; SZV
32K x 8 3.3V Static RAM
CY7C1399B
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05071 Rev. *A
Revised June 19, 2001
399B
Features
• Single 3.3V power supply
• Ideal for low-voltage cache memory applications
• High speed
— 10/12/15 ns
• Low active power
— 216 mW (max.)
• Low-power alpha immune 6T cell
• Plastic SOJ and TSOP packaging
Functional Description
The CY7C1399B is a high-performance 3.3V CMOS Static
RAM organized as 32,768 words by 8 bits. Easy memory ex-
pansion is provided by an active LOW Chip Enable (CE) and
active LOW Output Enable (OE) and three-state drivers. The
device has an automatic power-down feature, reducing the
power consumption by more than 95% when deselected.
An active LOW Write Enable signal (WE) controls the writing/
reading operation of the memory. When CE and WE inputs are
both LOW, data on the eight data input/output pins (I/O
0
through I/O
7
) is written into the memory location addressed by
the address present on the address pins (A
0
through A
14
).
Reading the device is accomplished by selecting the device
and enabling the outputs, CE and OE active LOW, while WE
remains inactive or HIGH. Under these conditions, the con-
tents of the location addressed by the information on address
pins is present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and Write Enable
(WE) is HIGH. The CY7C1399B is available in 28-pin standard
300-mil-wide SOJ and TSOP Type I packages.
Logic Block Diagram
Pin Configurations
1
2
3
4
5
6
7
8
9
10
11
14
15
16
20
19
18
17
21
24
23
22
Top View
SOJ
12
13
25
28
27
26
GND
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
WE
V
CC
A
4
A
3
A
2
A
1
I/O
7
I/O
6
I/O
5
I/O
4
A
14
A
5
I/O
0
I/O
1
I/O
2
CE
OE
A
0
I/O
3
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
ROW DECODE
R
SEN
SE AM
PS
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
CE
I/O
1
I/O
2
I/O
3
32K x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
9
A
0
A
11
A
13
A
12
A
14
A
10
Selection Guide
1399B-10
1399B-12
1399B-15
1399B-20
Maximum Access Time (ns)
10
12
15
20
Maximum Operating Current (mA)
60
55
50
45
Maximum CMOS Standby Current (
µ
A)
500
500
500
500
L
50
50
50
50
"Loading the manual" means you need to wait until the file loads and becomes available for online reading. Some manuals are very large, and the time they take to appear depends on your internet speed.
Summary
CY7C1399B Document #: 38-05071 Rev. *A Page 2 of 10 Maximum Ratings (Above which the useful life may be impaired. For user guide-lines, not tested.) Storage Temperature ................................. –65 ° C to +150 ° C Ambient Temperature withPower Applied ..........................................
CY7C1399B Document #: 38-05071 Rev. *A Page 4 of 10 Switching Characteristics Over the Operating Range [5] 1399B–10 1399B–12 Parameter Description Min. Max. Min. Max. Unit READ CYCLE t RC Read Cycle Time 10 12 ns t AA Address to Data Valid 10 12 ns t OHA Data Hold from Address Change 3 3 ns t ACE CE...
CY7C1399B Document #: 38-05071 Rev. *A Page 7 of 10 Notes: 13. Data I/O is high impedance if OE = V IH . 14. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.15. During this period, the I/Os are in the output state and input signals should not be applied. Swi...
