Cypress CY7C1381FV25 - Manual
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Table of Contents:
- Page 3 – Pin Configurations
- Page 5 – TMS
- Page 6 – Pin Definitions
- Page 7 – Functional Overview; Truth Table
- Page 8 – Interleaved Burst Address Table; DD; ZZ Mode Electrical Characteristics
- Page 11 – Disabling the JTAG Feature; TAP Controller State Diagram; Performing a TAP Reset; TAP Registers; Instruction Register
- Page 12 – Identification Register; TAP Instruction Set; Identification
- Page 13 – Reserved; TAP Timing
- Page 14 – TDO; TAP DC Electrical Characteristics And Operating Conditions
- Page 16 – 65-Ball BGA Boundary Scan Order; Ball ID; Internal
- Page 17 – Electrical Characteristics
- Page 19 – Switching Characteristics
- Page 20 – Timing Diagrams; Read Cycle Timing
- Page 21 – Write Cycle Timing
- Page 22 – Read/Write Cycle Timing
- Page 23 – ZZ Mode Timing; CLK
- Page 24 – Ordering Information; for actual products offered.
- Page 25 – Package Diagrams
- Page 28 – Document History Page; Change
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 38-05547 Rev. *E
Revised Feburary 14, 2007
Features
• Supports 133 MHz bus operations
• 512K x 36/1M x 18 common IO
• 2.5V core power supply (V
DD
)
• 2.5V IO supply (V
DDQ
)
• Fast clock-to-output times, 6.5 ns (133 MHz version)
• Provides high-performance 2-1-1-1 access rate
• User selectable burst counter supporting Intel
®
Pentium
®
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self timed write
• Asynchronous output enable
• CY7C1381DV25/CY7C1383DV25 available in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non
Pb-free 165-ball FBGA package.
CY7C1381FV25/CY7C1383FV25 available in Pb-free and
non Pb-free 119-ball BGA package
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• ZZ sleep mode option
Functional Description
The CY7C1381DV25/CY7C1383DV25/CY7C1381FV25/
CY7C1383FV25 is a 2.5V, 512K x 36 and 1M x 18
synchronous flow through SRAMs, designed to interface with
high-speed microprocessors with minimum glue logic.
Maximum access delay from clock rise is 6.5 ns (133 MHz
version). A 2-bit on-chip counter captures the first address in
a burst and increments the address automatically for the rest
of the burst access. All synchronous inputs are gated by
registers controlled by a positive edge triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, address pipelining chip enable (CE
1
), depth expansion
chip enables (CE
2
and
CE
3
), burst control inputs (ADSC,
ADSP, and ADV), write enables (BW
x
, and BWE), and global
write (GW). Asynchronous inputs include the output enable
(OE) and the ZZ pin.
The
CY7C1381DV25/CY7C1383DV25/CY7C1381FV25/
CY7C1383FV25 allows interleaved or linear burst sequences,
selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses can be initiated with the processor
address strobe (ADSP) or the cache controller address strobe
(ADSC) inputs. Address advancement is controlled by the
address advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or
address strobe controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the advance pin (ADV).
The CY7C1381DV25/CY7C1383DV25/CY7C1381FV25/
CY7C1383FV25 operates from a +2.5V core power supply
while all outputs also operate with a +2.5 supply. All inputs and
outputs are JEDEC-standard and JESD8-5-compatible.
Selection Guide
133 MHz
100 MHz
Unit
Maximum Access Time
6.5
8.5
ns
Maximum Operating Current
210
175
mA
Maximum CMOS Standby Current
70
70
mA
Notes
1. For best practices or recommendations, please refer to the Cypress application note AN1064,
SRAM System Design Guidelines
on
www.cypress.com
.
2. CE
3,
CE
2
are for TQFP and 165 FBGA package only. 119 BGA is offered only in 1 chip enable.
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Summary
CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev. *E Page 3 of 28 Pin Configurations A A A A A 1 A 0 NC NC V SS V DD A A A A A A A A DQP B DQ B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B DQ B V SS NCV DD ZZDQ A DQ A V DDQ V SSQ DQ A DQ A DQ A DQ A V SSQ V DDQ...
CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev. *E Page 5 of 28 Pin Configurations (continued) 165-Ball FBGA Pinout (3 Chip Enable) CY7C1381DV25 (512K x 36) 2 3 4 5 6 7 1 ABCD E F G H J K L M N P R TDO NC/288MNC/144M DQP C DQ C DQP D NC DQ D CE 1 BW B CE 3 BW C BWE A ...
CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document #: 38-05547 Rev. *E Page 6 of 28 Pin Definitions Name IO Description A 0 , A 1 , A Input- Synchronous Address inputs used to select one of the address locations . Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and C...
