Cypress CY7C1370DV25 - Manual
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Table of Contents:
- Page 2 – Selection Guide; Unit
- Page 3 – Pin Configurations
- Page 5 – TMS
- Page 6 – Pin Definitions
- Page 7 – Introduction
- Page 8 – DD; ZZ Mode Electrical Characteristics
- Page 10 – Disabling the JTAG Feature; TAP Controller State Diagram; Performing a TAP Reset; WE
- Page 11 – TAP Registers; ) when the BYPASS instruction is executed.; TAP Instruction Set; and t
- Page 12 – TAP Timing; Test Clock
- Page 13 – TAP AC Switching Characteristics
- Page 14 – TDO; TAP DC Electrical Characteristics And Operating Conditions
- Page 16 – 65-Ball FBGA Boundary Scan Order; Ball ID; Internal
- Page 17 – Electrical Characteristics
- Page 18 – Capacitance; Thermal Resistance; AC Test Loads and Waveforms
- Page 19 – Switching Characteristics
- Page 20 – Switching Waveforms
- Page 22 – Ordering Information; Commercial
- Page 23 – visit
- Page 24 – Package Diagrams
- Page 27 – Document History Page; Issue Date
18-Mbit (512K x 36/1M x 18)
Pipelined SRAM with NoBL™ Architecture
CY7C1370DV25
CY7C1372DV25
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 38-05558 Rev. *D
Revised June 29, 2006
Features
• Pin-compatible and functionally equivalent to ZBT™
• Supports 250-MHz bus operations with zero wait states
— Available speed grades are 250, 200 and 167 MHz
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write capability
• Single 2.5V core power supply (V
DD
)
• 2.5V I/O power supply (V
DDQ
)
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Available in JEDEC-standard lead-free 100-Pin TQFP,
lead-free and non-lead-free 119-Ball BGA and 165-Ball
FBGA packages
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• Burst capability—linear or interleaved burst order
• “ZZ” Sleep Mode option and Stop Clock option
Functional Description
The CY7C1370DV25 and CY7C1372DV25 are 2.5V, 512K x
36 and 1 Mbit x 18 Synchronous pipelined burst SRAMs with
No Bus Latency™ (NoBL
™)
logic, respectively. They are
designed to support unlimited true back-to-back Read/Write
operations with no wait states. The CY7C1370DV25 and
CY7C1372DV25 are equipped with the advanced (NoBL) logic
required to enable consecutive Read/Write operations with
data being transferred on every clock cycle. This feature
dramatically improves the throughput of data in systems that
require frequent Write/Read transitions. The CY7C1370DV25
and CY7C1372DV25 are pin-compatible and functionally
equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which when deasserted suspends operation and extends the
previous clock cycle.
Write operations are controlled by the Byte Write Selects
(BW
a
–BW
d
for CY7C1370DV25 and BW
a
–BW
b
for
CY7C1372DV25) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
A0, A1, A
C
MODE
BW
a
BW
b
WE
CE1
CE2
CE3
OE
READ LOGIC
DQs
DQP
a
DQP
b
DQP
c
DQP
d
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
MEMORY
ARRAY
E
E
INPUT
REGISTER 0
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC
A0'
A1'
D1
D0
Q1
Q0
A0
A1
C
ADV/LD
ADV/LD
E
INPUT
REGISTER 1
S
E
N
S
E
A
M
P
S
E
CLK
CEN
WRITE
DRIVERS
BW
c
BW
d
ZZ
SLEEP
CONTROL
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
Logic Block Diagram-CY7C1370DV25 (512K x 36)
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Summary
CY7C1370DV25CY7C1372DV25 Document #: 38-05558 Rev. *D Page 2 of 27 A0, A1, A C MODE BW a BW b WE CE1CE2CE3 OE READ LOGIC DQsDQP a DQP b D A T A S T E E R I N G O U T P U T B U F F E R S MEMORY ARRAY E E INPUT REGISTER 0 ADDRESS REGISTER 0 WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 WRITE REGIS...
CY7C1370DV25CY7C1372DV25 Document #: 38-05558 Rev. *D Page 3 of 27 Pin Configurations A A A A A 1 A 0 V SS V DD A A A A A A V DDQ V SS DQb DQb DQb V SS V DDQ DQb DQb V SS NC V DD DQaDQa V DDQ V SS DQaDQa V SS V DDQ V DDQ V SS DQc DQc V SS V DDQ DQc V DD V SS DQd DQd V DDQ V SS DQdDQdDQd V SS V DDQ A...
CY7C1370DV25CY7C1372DV25 Document #: 38-05558 Rev. *D Page 5 of 27 Pin Configurations (continued) 2 3 4 5 6 7 1 A B CD E F G H J K L M N P R TDO NC/576M NC/1G DQP c DQ c DQP d NC DQ d A CE 1 BW b CE 3 BW c CEN A CE2 DQ c DQ d DQ d MODE NC DQ c DQ c DQ d DQ d DQ d NC/36M NC/72M V DDQ BW d BW a CLK WE...
