Cypress CY7C1361C - Manual
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Table of Contents:
- Page 3 – Pin Configurations
- Page 6 – TMS
- Page 7 – Pin Definitions
- Page 9 – Functional Overview; Burst Sequences
- Page 12 – Disabling the JTAG Feature; through a pull-up resistor. TDO should be; TAP Controller State Diagram; Performing a TAP Reset; A RESET is performed by forcing TMS HIGH (V; TAP Registers; Instruction Register
- Page 13 – ) when the BYPASS instruction is executed.; TAP Instruction Set; and t
- Page 14 – TAP Timing; Test Clock
- Page 16 – Scan Register Sizes; Register Name; Identification Codes; Instruction
- Page 17 – 19-Ball BGA Boundary Scan Order
- Page 18 – 65-Ball FBGA Boundary Scan Order
- Page 19 – Electrical Characteristics
- Page 20 – Capacitance; Thermal Resistance; AC Test Loads and Waveforms
- Page 21 – Switching Characteristics
- Page 22 – Timing Diagrams; Read Cycle Timing
- Page 23 – Write Cycle Timing
- Page 24 – Read/Write Cycle Timing
- Page 25 – ZZ Mode Timing; CLK
- Page 26 – Ordering Information; Commercial
- Page 28 – Package Diagrams
- Page 31 – Document History Page; Issue Date
9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
CY7C1361C
CY7C1363C
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 38-05541 Rev. *F
Revised September 14, 2006
Features
• Supports 100, 133-MHz bus operations
• Supports 100-MHz bus operations (Automotive)
• 256K × 36/512K × 18 common I/O
• 3.3V –5% and +10% core power supply (V
DD
)
• 2.5V or 3.3V I/O power supply (V
DDQ
)
• Fast clock-to-output times
— 6.5 ns (133-MHz version)
• Provide high-performance 2-1-1-1 access rate
•
User-selectable burst counter supporting Intel
®
Pentium
®
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Available in lead-free 100-Pin TQFP package, lead-free
and non lead-free 119-Ball BGA package and 165-Ball
FBGA package
• TQFP Available with 3-Chip Enable and 2-Chip Enable
• IEEE 1149.1 JTAG-Compatible Boundary Scan
•“ZZ” Sleep Mode option
Functional Description
[1]
The CY7C1361C/CY7C1363C is a 3.3V, 256K x 36/512K x 18
Synchronous Flow-through SRAMs, respectively designed to
interface with high-speed microprocessors with minimum glue
logic. Maximum access delay from clock rise is 6.5 ns
(133-MHz version). A 2-bit on-chip counter captures the first
address in a burst and increments the address automatically
for the rest of the burst access. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE
1
), depth-expansion Chip Enables (CE
2
and CE
3
[2]
), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables (BW
x
,
and BWE), and Global Write (GW). Asynchronous inputs
include the Output Enable (OE) and the ZZ pin.
The CY7C1361C/CY7C1363C allows either interleaved or
linear burst sequences, selected by the MODE input pin. A
HIGH selects an interleaved burst sequence, while a LOW
selects a linear burst sequence. Burst accesses can be
initiated with the Processor Address Strobe (ADSP) or the
cache Controller Address Strobe (ADSC) inputs. Address
advancement is controlled by the Address Advancement
(ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
The CY7C1361C/CY7C1363C operates from a +3.3V core
power supply while all outputs may operate with either a +2.5
or +3.3V supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Selection Guide
133 MHz
100 MHz
Unit
Maximum Access Time
6.5
8.5
ns
Maximum Operating Current
250
180
mA
Maximum CMOS Standby Current
Comm/Ind’l
40
40
mA
Automotive
60
mA
Notes:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
2. CE
3
is for A version of TQFP (3 Chip Enable Option) and 165 FBGA package only. 119 BGA is offered only in 2 Chip Enable.
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Summary
CY7C1361CCY7C1363C Document #: 38-05541 Rev. *F Page 3 of 31 Pin Configurations A A A A A 1 A 0 NC NC V SS V DD NC A A A A A A A A DQP B DQ B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B DQ B V SS NCV DD ZZDQ A DQ A V DDQ V SSQ DQ A DQ A DQ A DQ A V SSQ V DDQ DQ A DQ A DQP A DQP C DQ C DQ C...
CY7C1361CCY7C1363C Document #: 38-05541 Rev. *F Page 6 of 31 Pin Configurations (continued) 165-Ball FBGA Pinout (3 Chip Enable) CY7C1361C (256K x 36) 2 3 4 5 6 7 1 A B CD E F G H J K L M N P R TDO NC/288M NC/144M DQP C DQ C DQP D NC DQ D CE 1 BW B CE 3 BW C BWE A CE 2 DQ C DQ D DQ D MODE NC DQ C DQ...
CY7C1361CCY7C1363C Document #: 38-05541 Rev. *F Page 7 of 31 Pin Definitions Name I/O Description A 0 , A 1 , A Input- Synchronous Address Inputs used to select one of the address location s. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE 1 , CE 2 , and CE 3 [2] are samp...
