Cypress CY7C1329H - Manual
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Table of Contents:
- Page 2 – Unit
- Page 3 – Pin Definitions
- Page 4 – Functional Overview; Single Read Accesses; Single Write Accesses Initiated by ADSP; Burst Sequences; Sleep Mode
- Page 5 – ZZ Mode Electrical Characteristics
- Page 7 – Truth Table for Read/Write
- Page 8 – Electrical Characteristics
- Page 9 – Capacitance; Thermal Resistance; AC Test Loads and Waveforms
- Page 10 – Switching Characteristics
- Page 11 – Switching Waveforms; Read Cycle Timing
- Page 12 – Write Cycle Timing
- Page 13 – Read/Write Cycle Timing
- Page 14 – ZZ Mode Timing; CLK
- Page 15 – Ordering Information; Commercial; Package Diagram
- Page 16 – Document History Page; Issue Date
2-Mbit (64K x 32) Pipelined Sync SRAM
CY7C1329H
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 38-05673 Rev. *B
Revised March 22, 2006
Features
• Registered inputs and outputs for pipelined operation
• 64K × 32 common I/O architecture
• 3.3V core power supply
• 2.5V/3.3V I/O operation
• Fast clock-to-output times
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel
®
Pentium
®
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Offered in JEDEC-standard lead-free 100-pin TQFP
package
• “ZZ” Sleep Mode Option
Functional Description
[1]
The CY7C1329H SRAM integrates 64K x 32 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE
1
), depth-expansion Chip Enables (CE
2
and
CE
3
), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW
[A:D]
and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle. This part supports Byte
Write operations (see Pin Descriptions and Truth Table for
further details). Write cycles can be one to four bytes wide as
controlled by the Byte Write control inputs. GW when active
LOW causes all bytes to be written.
The CY7C1329H operates from a +3.3V core power supply
while all outputs operate with either a +2.5V or +3.3V supply.
All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Note:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
Logic Block Diagram
ADDRESS
REGISTER
ADV
CLK
BURST
COUNTER
AND
LOGIC
CLR
Q1
Q0
ADSP
ADSC
MODE
BWE
GW
CE
1
CE
2
CE
3
OE
ENABLE
REGISTER
OUTPUT
REGISTERS
SENSE
AMPS
OUTPUT
BUFFERS
E
PIPELINED
ENABLE
INPUT
REGISTERS
A0, A1, A
BW
B
BW
C
BW
D
BW
A
MEMORY
ARRAY
D Q s
SLEEP
CONTROL
ZZ
A
[1:0]
2
DQ
A
BYTE
WRITE REGISTER
DQ
B
BYTE
WRITE REGISTER
DQ
C
BYTE
WRITE REGISTER
DQ
D
BYTE
WRITE REGISTER
DQ
A
BYTE
WRITE DRIVER
DQ
B
BYTE
WRITE DRIVER
DQ
C
BYTE
WRITE DRIVER
DQ
D
BYTE
WRITE DRIVER
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Summary
CY7C1329H Document #: 38-05673 Rev. *B Page 2 of 16 Pin Configuration Selection Guide 166 MHz 133 MHz Unit Maximum Access Time 3.5 4.0 ns Maximum Operating Current 240 225 mA Maximum CMOS Standby Current 40 40 mA A A A A A 1 A 0 N C /72M N C /36M V SS V DD NC /18M NC/9 M A A A A A A NC /4 M NCDQ B D...
CY7C1329H Document #: 38-05673 Rev. *B Page 3 of 16 Pin Definitions Name I/O Description A 0 , A 1 , A Input- Synchronous Address Inputs used to select one of the 64K address locations . Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE 1 , CE 2 , and CE 3 are sampled activ...
CY7C1329H Document #: 38-05673 Rev. *B Page 4 of 16 Functional Overview All synchronous inputs pass through input registers controlledby the rising edge of the clock. All data outputs pass throughoutput registers controlled by the rising edge of the clock. The CY7C1329H supports secondary cache in s...
