Cypress CY7C1324H - Manual
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Table of Contents:
- Page 2 – Selection Guide; Unit; Pin Configurations
- Page 3 – Pin Definitions
- Page 4 – Functional Overview; Burst Sequences
- Page 6 – Truth Table for Read/Write; Function; Read
- Page 7 – Electrical Characteristics
- Page 8 – Capacitance; Thermal Resistance; AC Test Loads and Waveforms
- Page 9 – Switching Characteristics
- Page 10 – Timing Diagrams; Read Cycle Timing
- Page 11 – Write Cycle Timing
- Page 13 – ZZ Mode Timing; CLK
- Page 14 – Ordering Information; Commercial; Package Diagram
- Page 15 – Document History Page; Issue Date
2-Mbit (128K x 18) Flow-Through Sync SRAM
CY7C1324H
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 001-00208 Rev. *B
Revised April 26, 2006
Features
• 128K x 18 common I/O
• 3.3V core power supply
• 3.3V/2.5V I/O supply
• Fast clock-to-output times
— 6.5 ns (133-MHz version)
• Provide high-performance 2-1-1-1 access rate
• User-selectable burst counter supporting Intel
®
Pentium
®
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Offered in JEDEC-standard lead-free 100-pin TQFP
package
• “ZZ” Sleep Mode option
Functional Description
[1]
The CY7C1324H is a 128K x 18 synchronous cache RAM
designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
6.5 ns (133-MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automati-
cally for the rest of the burst access. All synchronous inputs
are gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE
1
), depth-expansion Chip Enables (CE
2
and
CE
3
), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW
[A:B]
, and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin. The
CY7C1324H allows either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects
an interleaved burst sequence, while a LOW selects a linear
burst sequence. Burst accesses can be initiated with the
Processor Address Strobe (ADSP) or the cache Controller
Address Strobe (ADSC) inputs. Address advancement is
controlled by the Address Advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
The CY7C1324H operates from a +3.3V core power supply
while all outputs may operate with either a +3.3V or +2.5V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Note:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
ADDRESS
REGISTER
ADV
CLK
BURST
COUNTER AND
LOGIC
CLR
Q1
Q0
ADSC
CE
1
OE
SENSE
AMPS
MEMORY
ARRAY
ADSP
OUTPUT
BUFFERS
INPUT
REGISTERS
MODE
CE
2
CE
3
GW
BWE
A0,A1,A
BW
B
BW
A
DQ
B
,DQP
B
WRITE REGISTER
DQ
A
,DQP
A
WRITE REGISTER
ENABLE
REGISTER
A[1:0]
DQs
DQP
A
DQP
B
DQ
B
,DQP
B
WRITE DRIVER
DQ
A
,DQP
A
WRITE DRIVER
SLEEP
CONTROL
ZZ
Logic Block Diagram
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Summary
CY7C1324H Document #: 001-00208 Rev. *B Page 2 of 15 Selection Guide 133 MHz Unit Maximum Access Time 6.5 ns Maximum Operating Current 225 mA Maximum Standby Current 40 mA Pin Configurations 100-pin TQFP Pinout A A A A A 1 A 0 NC /72M NC /36M V SS V DD NC/9M A A A A A NC/4M A NC V DDQ V SS NC DQP B ...
CY7C1324H Document #: 001-00208 Rev. *B Page 3 of 15 Pin Definitions Name I/O Description A0, A1, A Input- Synchronous Address Inputs used to select one of the 128K address location s. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE 1 , CE 2 , and CE 3 are sampled active....
CY7C1324H Document #: 001-00208 Rev. *B Page 4 of 15 Functional Overview All synchronous inputs pass through input registers controlledby the rising edge of the clock. Maximum access delay fromthe clock rise (t CDV ) is 6.5 ns (133-MHz device). The CY7C1324H supports secondary cache in systemsutiliz...
