Cypress CY7C131A - Manual
Cypress CY7C131A – Manual, read for free online in PDF format. We hope this helps you resolve any issues you may have. If you have further questions, please contact us through the contact form.
Table of Contents:
- Page 2 – Pin Configurations
- Page 3 – Pin Definitions; Left Port; Selection Guide; Parameter
- Page 4 – Electrical Characteristics
- Page 5 – Capacitance; Input Capacitance; pF; Output Capacitance
- Page 6 – Switching Characteristics
- Page 9 – Switching Waveforms; Either Port Address Access
- Page 10 – Either Port
- Page 11 – CE
- Page 12 – BUSY
- Page 13 – Figure 13. Interrupt Timing Diagrams; Right Side Clears INT
- Page 14 – Typical DC and AC Characteristics; NORMALIZED SUPPLY CURRENT
- Page 15 – Ordering Information
- Page 17 – Package Diagrams
- Page 19 – Document History Page; Worldwide Sales and Design Support; Change
CY7C130, CY7C130A
CY7C131, CY7C131A
CY7C140, CY7C141
1K x 8 Dual-Port Static RAM
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 38-06002 Rev. *E
Revised December 09, 2008
Features
■
True dual-ported memory cells, which allow simultaneous
reads of the same memory location
■
1K x 8 organization
■
0.65 micron CMOS for optimum speed and power
■
High speed access: 15 ns
■
Low operating power: I
CC
= 110 mA (maximum)
■
Fully asynchronous operation
■
Automatic power down
■
Master CY7C130/130A/CY7C131/131A easily expands data
bus width to 16 or more bits using slave CY7C140/CY7C141
■
BUSY output flag on CY7C130/130A/CY7C131/131A; BUSY
input on CY7C140/CY7C141
■
INT flag for port-to-port communication
■
Available in 48-pin DIP (CY7C130/130A/140), 52-pin PLCC,
52-pin TQFP
■
Pb-free packages available
Functional Description
The CY7C130/130A/CY7C131/131A/CY7C140
[1]
and CY7C141
are high speed CMOS 1K by 8 dual-port static RAMs. Two ports
are provided permitting independent access to any location in
memory. The CY7C130/130A/ CY7C131/131A can be used as
either a standalone 8-bit dual-port static RAM or as a master
dual-port RAM in conjunction with the CY7C140/CY7C141 slave
dual-port device in systems requiring 16-bit or greater word
widths. It is the solution to applications requiring shared or
buffered data, such as cache memory for DSP, bit-slice, or multi-
processor designs.
Each port has independent control pins; chip enable (CE), write
enable (R/W), and output enable (OE). Two flags are provided
on each port, BUSY and INT. BUSY signals that the port is trying
to access the same location currently being accessed by the
other port. INT is an interrupt flag indicating that data is placed
in a unique location (3FF for the left port and 3FE for the right
port). An automatic power down feature is controlled indepen-
dently on each port by the chip enable (CE) pins.
The CY7C130/130A and CY7C140 are available in 48-pin DIP.
The CY7C131/131A and CY7C141 are available in 52-pin
PLCC, 52-pin Pb-free PLCC, 52-pin PQFP, and 52-pin Pb-free
PQFP.
R/W
L
BUSY
L
CE
L
OE
L
A
9L
A
0L
A
0R
A
9R
R/W
R
CE
R
OE
R
CE
R
OE
R
CE
L
OE
L
R/W
L
R/W
R
I/O
7L
I/O
0L
I/O
7R
I/O
0R
BUSY
R
INT
L
INT
R
ARBITRATION
LOGIC
(7C130/7C131 ONLY)
AND
INTERRUPT LOGIC
CONTROL
I/O
CONTROL
I/O
MEMORY
ARRAY
ADDRESS
DECODER
ADDRESS
DECODER
[2]
[3]
Logic Block Diagram
Notes
1. CY7C130 and CY7C130A are functionally identical; CY7C131 and CY7C131A are functionally identical.
2. CY7C130/130A/CY7C131/131A (Master): BUSY is open drain output and requires pull-up resistor.
CY7C140/CY7C141 (Slave): BUSY is input.
3. Open drain outputs: pull-up resistor required.
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Summary
CY7C130, CY7C130ACY7C131, CY7C131A CY7C140, CY7C141 Document #: 38-06002 Rev. *E Page 2 of 19 Pin Configurations Figure 1. Pin Diagram - DIP (Top View) Figure 2. Pin Diagram - PLCC (Top View) Figure 3. Pin Diagram - PQFP (Top View) 1314151617181920212223 26 27 28 32313029 33 363534 24 25 GND 1234567...
CY7C130, CY7C130ACY7C131, CY7C131A CY7C140, CY7C141 Document #: 38-06002 Rev. *E Page 3 of 19 Pin Definitions Left Port Right Port Description CE L CE R Chip Enable R/W L R/W R Read/Write Enable OE L OE R Output Enable A 0L –A 11/12L A 0R –A 11/12R Address I/O 0L –I/O 15/17L I/O 0R –I/O 15/17R Data ...
CY7C130, CY7C130ACY7C131, CY7C131A CY7C140, CY7C141 Document #: 38-06002 Rev. *E Page 4 of 19 Maximum Ratings [5] Exceeding maximum ratings may shorten the useful life of thedevice. User guidelines are not tested. Storage Temperature ................................. –65 ° C to +150 ° C Ambient Temp...
