Cypress CY7C1316CV18 - Manual
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Table of Contents:
- Page 2 – rray
- Page 3 – Array
- Page 4 – Pin Configuration
- Page 6 – Pin Definitions; Application Example
- Page 8 – Functional Overview; Write Operations
- Page 9 – with V; Echo Clocks; Switching; DLL; DLL Considerations in QDRIITM/DDRII; Figure 1; Figure 1. Application Example; ohms; BUS
- Page 10 – Write Cycle Descriptions
- Page 12 – Disabling the JTAG Feature; Test Access Port—Test Clock; TAP Registers; Instruction Register; Boundary Scan Register; TAP Instruction Set
- Page 13 – and t; ). The SRAM clock input might not be captured
- Page 14 – TAP Controller State Diagram; The state diagram for the TAP controller follows.; RESET
- Page 16 – Figure 2
- Page 18 – Boundary Scan Order; Bump ID; Internal
- Page 19 – Power Up Sequence in DDR-II SRAM; Power Up Sequence; Figure 3. Power Up Waveforms
- Page 20 – Maximum Ratings; Operating Range; DC Electrical Characteristics
- Page 21 – AC Electrical Characteristics
- Page 22 – Capacitance; Thermal Resistance
- Page 23 – Switching Characteristics
- Page 25 – Switching Waveforms; LD; CQD
- Page 26 – Ordering Information; for actual products offered.
- Page 28 – Package Diagram
- Page 29 – Document History Page; Submission
18-Mbit DDR-II SRAM 2-Word
Burst Architecture
CY7C1316CV18, CY7C1916CV18
CY7C1318CV18, CY7C1320CV18
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document Number: 001-07160 Rev. *E
Revised June 18, 2008
Features
■
18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36)
■
267 MHz clock for high bandwidth
■
2-word burst for reducing address bus frequency
■
Double Data Rate (DDR) interfaces
(data transferred at 534 MHz) at 267 MHz
■
Two input clocks (K and K) for precise DDR timing
❐
SRAM uses rising edges only
■
Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
■
Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
■
Synchronous internally self-timed writes
■
DDR-II operates with 1.5 cycle read latency when the DLL is
enabled
■
Operates similar to a DDR-I device with 1 cycle read latency in
DLL off mode
■
1.8V core power supply with HSTL inputs and outputs
■
Variable drive HSTL output buffers
■
Expanded HSTL output voltage (1.4V–V
DD
)
■
Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)
■
Offered in both Pb-free and non Pb-free packages
■
JTAG 1149.1 compatible test access port
■
Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1316CV18 – 2M x 8
CY7C1916CV18 – 2M x 9
CY7C1318CV18 – 1M x 18
CY7C1320CV18 – 512K x 36
Functional Description
The CY7C1316CV18, CY7C1916CV18, CY7C1318CV18, and
CY7C1320CV18 are 1.8V Synchronous Pipelined SRAMs
equipped with DDR-II architecture. The DDR-II consists of an
SRAM core with advanced synchronous peripheral circuitry and
a one-bit burst counter. Addresses for read and write are latched
on alternate rising edges of the input (K) clock. Write data is
registered on the rising edges of both K and K. Read data is
driven on the rising edges of C and C if provided, or on the rising
edge of K and K if C/C are not provided. Each address location
is associated with two 8-bit words in the case of CY7C1316CV18
and two 9-bit words in the case of CY7C1916CV18 that burst
sequentially into or out of the device. The burst counter always
starts with a ‘0’ internally in the case of CY7C1316CV18 and
CY7C1916CV18. For CY7C1318CV18 and CY7C1320CV18,
the burst counter takes in the least significant bit of the external
address and bursts two 18-bit words (in the case of
CY7C1318CV18) of two 36-bit words (in the case of
CY7C1320CV18) sequentially into or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs, D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need to capture data
separately from each individual DDR SRAM in the system
design. Output data clocks (C/C) enable maximum system
clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Selection Guide
Description
267 MHz
250 MHz
200 MHz
167 MHz
Unit
Maximum Operating Frequency
267
250
200
167
MHz
Maximum Operating Current
x8
775
705
575
490
mA
x9
780
710
580
490
x18
805
730
600
510
x36
855
775
635
540
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Summary
CY7C1316CV18, CY7C1916CV18CY7C1318CV18, CY7C1320CV18 Document Number: 001-07160 Rev. *E Page 2 of 29 Logic Block Diagram (CY7C1316CV18) Logic Block Diagram (CY7C1916CV18) WriteReg WriteReg CLK A (19:0) Gen. K K Control Logic Address Register Read Add . Decode Read Data Reg. R/W Output Logic Reg. Reg...
CY7C1316CV18, CY7C1916CV18CY7C1318CV18, CY7C1320CV18 Document Number: 001-07160 Rev. *E Page 3 of 29 Logic Block Diagram (CY7C1318CV18) Logic Block Diagram (CY7C1320CV18) WriteReg WriteReg CLK A (19:0) Gen. K K Control Logic Address Register Read Add . Decode Read Data Reg. R/W Output Logic Reg. Reg...
CY7C1316CV18, CY7C1916CV18CY7C1318CV18, CY7C1320CV18 Document Number: 001-07160 Rev. *E Page 4 of 29 Pin Configuration The pin configuration for CY7C1316CV18, CY7C1916CV18, CY7C1318CV18, and CY7C1320CV18 follow. [1] 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1316CV18 (2M x 8) 1 2 3 4 5 6 7 8 9 10 1...
