Cypress CY7C1298H - Manual
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Table of Contents:
- Page 2 – Functional Block Diagram; BURST
- Page 3 – Pin Configurations; Top View
- Page 4 – Pin Descriptions
- Page 5 – Functional Overview; Single Read Accesses; Single Write Accesses Initiated by ADSP; Burst Sequences
- Page 6 – Truth Table
- Page 8 – Electrical Characteristics
- Page 9 – Capacitance; Thermal Characteristics; AC Test Loads and Waveforms
- Page 10 – Switching Characteristics
- Page 11 – Switching Waveforms; Read Timing
- Page 12 – Write Timing
- Page 14 – ZZ Mode Timing; CLK
- Page 15 – Ordering Information; Commercial; Package Diagram
- Page 16 – Document History Page; Issue Date
1-Mbit (64K x 18) Pipelined DCD Sync SRAM
CY7C1298H
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 38-05665 Rev. *B
Revised July 5, 2006
Features
• Registered inputs and outputs for pipelined operation
• Optimal for performance (Double-Cycle deselect)
— Depth expansion without wait state
• 64K × 18-bit common I/O architecture
• 3.3V core power supply (V
DD
)
• 2.5V/3.3V I/O power supply (V
DDQ
)
• Fast clock-to-output times
— 3.5 ns (for 166-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel
®
Pentium
®
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous Output Enable
• Available in JEDEC-standard lead-free 100-Pin TQFP
package
• “ZZ” Sleep Mode option
Functional Description
[1]
The CY7C1298H SRAM integrates 64K x 18 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE
1
), depth-expansion Chip Enables (CE
2
and CE
3
), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW
[A:B]
, and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two bytes wide as
controlled by the byte write control inputs. GW active LOW
causes all bytes to be written. This device incorporates an
additional pipelined enable register which delays turning off
the output buffers an additional cycle when a deselect is
executed.This feature allows depth expansion without penal-
izing system performance.
The CY7C1298H operates from a +3.3V core power supply
while all outputs operate either with a +2.5V or +3.3V supply.
All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Selection Guide
166 MHz
133 MHz
Unit
Maximum Access Time
3.5
4.0
ns
Maximum Operating Current
240
225
mA
Maximum CMOS Standby Current
40
40
mA
Note:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
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Summary
CY7C1298H Document #: 38-05665 Rev. *B Page 2 of 16 Functional Block Diagram ADDRESSREGISTER ADV CLK BURST COUNTER AND LOGIC CLR Q1 Q0 ADSC BW B BW A CE 1 DQ B, DQP B BYTE WRITE REGISTER DQ A , DQP A BYTE WRITE REGISTER ENABLE REGISTER OE SENSE AMPS MEMORY ARRAY ADSP 2 A [1:0] MODE CE 2 CE 3 GW BWE ...
CY7C1298H Document #: 38-05665 Rev. *B Page 3 of 16 Pin Configurations 100-Pin TQFP Top View ANCNCV DDQ V SSQ NCDQP A DQ A DQ A V SSQ V DDQ DQ A DQ A V SS NCV DD ZZDQ A DQ A V DDQ V SSQ DQ A DQ A NCNCV SSQ V DDQ NCNCNC NCNCNC V DDQ V SSQ NCNC DQ B DQ B V SSQ V DDQ DQ B DQ B V DD NC V SS DQ B DQ B V ...
CY7C1298H Document #: 38-05665 Rev. *B Page 4 of 16 Pin Descriptions Pin Type Description A0, A 1 , A Input- Synchronous Address Inputs used to select one of the 64K address locations . Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE 1 , CE 2 , and CE 3 are sampled active...
