Cypress CY7C1041DV33 - Manual
Cypress CY7C1041DV33 – Manual, read for free online in PDF format. We hope this helps you resolve any issues you may have. If you have further questions, please contact us through the contact form.
Table of Contents:
- Page 2 – Selection Guide; Description; Pin Configuration
- Page 3 – DC Electrical Characteristics
- Page 4 – Capacitance; Input Capacitance; pF; IO Capacitance; Thermal Resistance; The AC test loads and waveform diagram follows.
- Page 5 – AC Switching Characteristics
- Page 7 – Switching Waveforms
- Page 10 – Ordering Information; Industrial; Package Diagrams
- Page 12 – Document History Page; Change
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 38-05473 Rev. *E
Revised July 17, 2008
CY7C1041DV33
4 Mbit (256K x 16) Static RAM
Features
■
Pin and function compatible with CY7C1041CV33
■
High speed
❐
t
AA
= 10 ns
■
Low active power
❐
I
CC
= 90 mA at 10 ns (industrial)
■
Low CMOS standby power
❐
I
SB2
= 10 mA
■
2.0V data retention
■
Automatic power down when deselected
■
TTL compatible inputs and outputs
■
Easy memory expansion with CE and OE features
■
Available in Pb-free 48-ball VFBGA, 44-pin (400-mil) molded
SOJ, and 44-pin TSOP II packages
Functional Description
The CY7C1041DV33
is a high performance CMOS Static RAM
organized as 256K words by 16 bits. To write to the device, take
Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte
LOW Enable (BLE) is LOW, then data from IO pins (IO
0
to IO
7
)
is written into the location specified on the address pins (A
0
to
A
17
). If Byte HIGH Enable (BHE) is LOW, then data from IO pins
(IO
8
to IO
15
) is written into the location specified on the address
pins (A
0
to A
17
).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
BLE is LOW, then data from the memory location specified by
the address pins appears on IO
0
to IO
7
. If BHE is LOW, then data
from memory appears on IO
8
to IO
15
. See the
page 9 for a complete description of read and write modes.
The input and output pins (IO
0
to IO
15
) are placed in a high
impedance state when the device is deselected (CE HIGH),
outputs are disabled (OE HIGH), BHE and BLE are disabled
(BHE, BLE HIGH), or during a write operation (CE LOW and WE
LOW).
The CY7C1041DV33 is available in a standard 44-pin 400-mil
wide SOJ and 44-pin TSOP II package with center power and
ground (revolutionary) pinout and a 48-ball fine-pitch ball grid
array (FBGA) package.
14
15
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
RO
W DE
CO
DE
R
S
E
N
SE AM
PS
INPUT BUFFER
256K × 16
A
0
A
11
A
13
A
12
A
A
A
16
A
17
A
9
A
10
IO
0
–IO
7
OE
IO
8
–IO
15
CE
WE
BLE
BHE
Logic Block Diagram
Note
1. For guidelines on SRAM system design, refer to the “System Design Guidelines” Cypress application note, available at www.cypress.com.
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Summary
CY7C1041DV33 Document #: 38-05473 Rev. *E Page 2 of 13 Selection Guide Description –10 (Industrial) –12 (Automotive) [2] Unit Maximum Access Time 10 12 ns Maximum Operating Current 90 95 mA Maximum CMOS Standby Current 10 15 mA Pin Configuration Figure 1. 44-Pin SOJ/TSOP II Figure 2. 48-Ball VFBGA (...
CY7C1041DV33 Document #: 38-05473 Rev. *E Page 3 of 13 Maximum Ratings Exceeding maximum ratings may shorten the useful life of thedevice. These user guidelines are not tested. Storage Temperature ................................. –65 ° C to +150 ° C Ambient Temperature withPower Applied ..............
CY7C1041DV33 Document #: 38-05473 Rev. *E Page 4 of 13 Capacitance [6] Parameter Description Test Conditions Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V CC = 3.3V 8 pF C OUT IO Capacitance 8 pF Thermal Resistance [6] Parameter Description Test Conditions FBGA Package SOJ Package TSOP ...
