Cypress CY7C1018CV33 - Manual
Cypress CY7C1018CV33 – Manual, read for free online in PDF format. We hope this helps you resolve any issues you may have. If you have further questions, please contact us through the contact form.
Table of Contents:
- Page 2 – Electrical Characteristics
- Page 3 – Parameter
- Page 4 – Switching Waveforms
- Page 5 – CE; Data Out; Data In; Selected, Outputs Disabled
- Page 6 – Commercial
- Page 7 – Document History Page; Issue
128K x 8 Static RAM
CY7C1018CV33
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 38-05131 Rev. *D
Revised August 3, 2006
Features
• Pin- and function-compatible with CY7C1018BV33
• High speed
— t
AA
= 10 ns
• CMOS for optimum speed/power
• Center power/ground pinout
• Data retention at 2.0V
• Automatic power-down when deselected
• Easy memory expansion with CE
and OE options
• Available in Pb-free and non Pb-free 300-mil-wide
32-pin SOJ
Functional Description
[1]
The CY7C1018CV33 is a high-performance CMOS static
RAM organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and tri-state drivers. This
device has an automatic power-down feature that significantly
reduces power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O
0
through I/O
7
) is then written into the location
specified on the address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1018CV33 is available in a standard 300-mil-wide
SOJ.
Note:
1.
For guidelines on SRAM system designs, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
14
15
Logic Block Diagram
Pin Configurations
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
ROW DE
CODER
SENSE A
M
PS
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
I/O
1
I/O
2
I/O
3
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
11
A
13
A
12
A
A
10
CE
A
A
16
A
9
1
2
3
4
5
6
7
8
9
10
11
14
19
20
24
23
22
21
25
28
27
26
Top View
SOJ
12
13
29
32
31
30
16
15
17
18
A
7
A
1
A
2
A
3
CE
I/O
0
I/O
1
V
CC
A
13
A
16
A
15
OE
I/O
7
I/O
6
A
12
A
11
A
10
A
9
I/O
2
A
0
A
4
A
5
A
6
I/O
4
V
CC
I/O
5
A
8
I/O
3
WE
V
SS
A
14
V
SS
128K x 8
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Summary
CY7C1018CV33 Document #: 38-05131 Rev. *D Page 2 of 7 Maximum Ratings (Above which the useful life may be impaired. For user guide-lines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature withPower Applied ............................................
CY7C1018CV33 Document #: 38-05131 Rev. *D Page 3 of 7 AC Test Loads and Waveforms [4] Switching Characteristics Over the Operating Range [5] Parameter Description -10 -12 -15 Unit Min. Max. Min. Max. Min. Max. Read Cycle t RC Read Cycle Time 10 12 15 ns t AA Address to Data Valid 10 12 15 ns t OHA D...
CY7C1018CV33 Document #: 38-05131 Rev. *D Page 4 of 7 Switching Waveforms Read Cycle No. 1 [11, 12] Read Cycle No. 2 (OE Controlled) [12, 13] Write Cycle No. 1 (CE Controlled) [14, 15] Notes: 11. Device is continuously selected. OE, CE = V IL . 12. WE is HIGH for Read cycle.13. Address valid prior t...
