Cypress CY7C0852AV - Manual
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Table of Contents:
- Page 2 – Logic Block Diagram; True
- Page 3 – Pin Configurations
- Page 6 – Pin Definitions
- Page 7 – Table 2
- Page 8 – counter register; Table 3; Counter Reset Operation; Figure 4; Counter Increment Operation; Figure 5; Counter Hold Operation
- Page 11 – Figure 5. Programmable Counter-Mask Register Operation
- Page 12 – Performing a TAP Reset
- Page 13 – Electrical Characteristics
- Page 14 – Switching Characteristics; ALL INPUT PULSES; OUTPUT
- Page 16 – JTAG Timing
- Page 17 – Switching Waveforms; Figure 8. Master Reset
- Page 18 – Figure 10. Bank Select Read
- Page 19 – Figure 13. Read with Address Counter Advance
- Page 20 – Figure 14. Write with Address Counter Advance
- Page 23 – Figure 19. Counter Reset
- Page 24 – Figure 20. Readback State of Address Counter or Mask Register
- Page 26 – Figure 22. Counter Interrupt and Retransmit
- Page 27 – Write; Read; CLK
- Page 28 – Ordering Information
- Page 29 – Package Diagrams
- Page 31 – Document History Page; Synchronous Dual-Port RAM
FLEx36™ 3.3V 32K/64K/128K/256K x 36
Synchronous Dual-Port RAM
CY7C0850AV, CY7C0851AV
CY7C0852AV, CY7C0853AV
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 38-06070 Rev. *H
Revised July 29, 2008
Features
■
True dual-ported memory cells that allow simultaneous access
of the same memory location
■
Synchronous pipelined operation
■
Organization of 1-Mbit, 2-Mbit, 4-Mbit, and 9-Mbit devices
■
Pipelined output mode allows fast operation
■
0.18-micron CMOS for optimum speed and power
■
High-speed clock to data access
■
3.3V low power
❐
Active as low as 225 mA (typ)
❐
Standby as low as 55 mA (typ)
■
Mailbox function for message passing
■
Global master reset
■
Separate byte enables on both ports
■
Commercial and industrial temperature ranges
■
IEEE 1149.1-compatible JTAG boundary scan
■
172-Ball FBGA (1 mm pitch) (15 mm × 15 mm)
■
176-Pin TQFP (24 mm × 24 mm × 1.4 mm)
■
Counter wrap around control
❐
Internal mask register controls counter wrap-around
❐
Counter-interrupt flags to indicate wrap-around
❐
Memory block retransmit operation
■
Counter readback on address lines
■
Mask register readback on address lines
■
Dual Chip Enables on both ports for easy depth expansion
Functional Description
The FLEx36™ family includes 1M, 2M, 4M, and 9M pipelined,
synchronous, true dual-port static RAMs that are high-speed,
low-power 3.3V CMOS. Two ports are provided, permitting
independent, simultaneous access to any location in memory.
The result of writing to the same location by more than one port
at the same time is undefined. Registers on control, address, and
data lines allow for minimal setup and hold time.
During a Read operation, data is registered for decreased cycle
time. Each port contains a burst counter on the input address
register. After externally loading the counter with the initial
address, the counter increments the address internally (more
details to follow). The internal Write pulse width is independent
of the duration of the R/W input signal. The internal Write pulse
is self-timed to allow the shortest possible cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle powers down
the internal circuitry to reduce the static power consumption. One
cycle with chip enables asserted is required to reactivate the
outputs.
Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
control the counter wrap-around, counter interrupt (CNTINT)
flags, readback of mask register value on address lines,
retransmit functionality, interrupt flags for message passing,
JTAG for boundary scan, and asynchronous Master Reset
(MRST).
The CY7C0853AV device in this family has limited features.
Please see
See “Address Counter and Mask Register
for details.
Table 1. Product Selection Guide
Density
1-Mbit
(32K x 36)
2-Mbit
(64K x 36)
4-Mbit
(128K x 36)
9-Mbit
(256K x 36)
Part Number
CY7C0850AV
CY7C0851AV
CY7C0852AV
CY7C0853AV
Max. Speed (MHz)
167
167
167
133
Max. Access Time - Clock to Data (ns)
4.0
4.0
4.0
4.7
Typical operating current (mA)
225
225
225
270
Package
176TQFP
172FBGA
176TQFP
172FBGA
176TQFP
172FBGA
172FBGA
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Summary
CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Document #: 38-06070 Rev. *H Page 2 of 32 Logic Block Diagram [1] A 0L –A 17L CLK L ADS L CNTEN L CNTRST L True RAM Array 18 Addr. Read Back CNTINT L Mask Register Counter/ Address Register CNT/MSK L Address Decode Dual-Ported Interrupt Logic INT L Reset...
CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Document #: 38-06070 Rev. *H Page 3 of 32 Pin Configurations Figure 1. 172-Ball BGA (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A DQ32L DQ30L CNTINTL VSS DQ13L VDD DQ11L DQ11R VDD DQ13R VSS CNTINTR DQ30R DQ32R B A0L DQ33L DQ29L DQ17L DQ14L DQ12L DQ9L DQ9...
CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Document #: 38-06070 Rev. *H Page 6 of 32 Pin Definitions Left Port Right Port Description A 0L –A 17L [1] A 0R –A 17R [1] Address Inputs . ADS L [3] ADS R [3] Address Strobe Input . Used as an address qualifier. This signal should be asserted LOW for th...
